MiSTer FPGA Forum

ExCyber, thanks for the reply, what you say makes a lot of sense. I converted both my RAM and my register file into Altera objects and it drastically reduced the number of registers consumed in the design (it also kept me honest so I wasn't doing things like reading and writing the same register in the same machine cycle). I used a dual-port RAM fo...

Turns out using functions and tasks was fine... the real issue was my dodgy RAM instantiation. Using the wizard to instantiate an Altera block ram solved all my problems.

Incidentally, I found that wrapping sys_top.v to instantiate just my own test module was a significant win on iteration time.

Bonus failure -- I was trying to keep everything in one file, and Verilator complains about multiple modules in the same file, so I tried using functions and tasks to achieve my result. Somehow this caused fitting to fail. Inlining everything in a master "cpu" module seemed to work.

Apparently instantiating a 64k ram (reg [15:0] ram[32768) really upsets the synthesis software and sends it to the brink of insanity.

I've seen other cores use some sort of wizard to instantiate a large ram, or I need to hook it up to the MiSTer SRAM interface.

-Dave

I got my 16-bit cpu implemented and passing Verilator lint tests, but it crashed Quartus any time I tried to compile (I instantiated my cpu in the mycore template MiSTer project). I eventually realized that you can't have a given register driven by more than one thing at the same time (that's why register files and rams are generally implemented wi...

I just realized the add of offset probably needs to be in the third state because it’s dependent on the register read.

These aren't MiSTer specific per se, but I'd be developing my code under the MiSTer framework since it gives me input and output support, and I figure some of the folks around here are further along the journey than I am. I'm trying to implement a CPU of my own design from scratch (google j1 forth cpu for a really great example). At this point it's...

Either directly to the DE10 nano mainboard, or perhaps to something on the I/O board?

Most/all cores have a ps2_key input and it would be cool to drive that directly instead of coming through the ARM chip.

Thanks,

-Dave

Interesting. I can confirm that even the Template core still takes a few minutes to iterate on. Maybe some sort of "minimal MiSTer" configuration define would be useful? Essentially it turns off everything except VGA and... something... PS/2 keyboard support has got to be pretty simple. I don't know what other parts are expensive to build...

I was planning on coding in verilog (I've been programming professionally in C/C++ for 30 years) and the Steven Hugg book uses verilog... but most of the MiSTer cores are written predominantly in VHDL, so... haven't decided yet I guess. Interestingly, the sample core, Template_MiSTer-master, is written in Verilog/System Verilog. That's actually the...

Something I'd love to see, for the sake of understanding, is something super basic like composite or VGA video output to some GPIO pins and direct connection to a PS/2 style keyboard, but I think that's more of a "DE10 Nano" issue than a "MiSTer" issue. What the MiSTer codebase gives us is a consistent, abstracted framework wher...

I was asking similar questions a few days ago. Some things I've been able to figure out that might not be obvious to a newcomer: 1. Everything under sys/ is intended to be the same across all emu cores. Stuff in here is the OSD, dealing with inputs, and VGA and HDMI output. 2. sys/sys_top,v is actually part of this code. It controls several things ...

...and now it suddenly started working. Only thing I did was put the virtualized Windows session in full screen mode.

Turns out they have a free 14 day trial, so I gave it a shot. It installed quite easily and used by existing bootcamp partition. And while it recognized me plugging my DE10-Nano kit in via USB, the Programmer seems to think there's no hardware no matter what I try, which makes iteration and debugging challenging. I've sent in a support request to P...

So I’m guessing that for the NES core I’m going to need to strip the header off the .nes file I’m using?

Thanks again for your help!

Dave

Is any of this documented anywhere? I tried to make a boot.rom for phoenix and placed it in \games\a.phoenix but it didn't work either. Based on the MRA file it looked like it was just the concatenation of 12 2k files.

I changed Settings / Compiler Settings / Optimization mode from Performance (High Effort) to Balanced (Normal flow). It didn't really help A&S at all (took 3:19) or the fitter for that matter (took 9:02). Total time was 12:53. I changed Settings / Compiler Settings / Advanced Analysis & Sythesis Settings / Synthesis Effort to Fast and Advan...

Just the Lite version, and leaving something like that out of the free version doesn't surprise me. I'll play with some of the other settings though and see if they help. The fitter seems to be the real pig.

I was digging up the specs on the System Y board (Power Drift) and holy heck it has three m68k's on it. Do we have enough room on a Cyclone V to instantiate three of them and all the sprite hardware?

This article looks useful (ways to improve compilation time)

https://www.intel.com/content/dam/www/p ... i52022.pdf

-Dave

@JaguarLV, thank you, that worked for bagman! It's confusing because the layout for boot.rom files doesn't seem to match the suggested layout for the RBF and MRA files.

I copied super Mario bros into \games\NES\boot.rom but it didn't work there for some reason, does it need to have its header stripped first somehow?

-Dave

Hmm... just noticed your qualifier of "except for cores that don't do much..." I ran a clean.bat in the NES core and then built that from scratch (I couldn't figure out if it supported disabling HDMI, there certainly wan't a DEBUG_NOHDMI symbol I could find) A&S :3:06, Fitter: 9:54, total time was 13:19 Without a way to disable HDMI i...

Regarding synthesis time... I have a recent MacBookPro (8x2 cores, i9 I think but mobile not desktop obviously). I tried the Template project, and on first compile (mm:ss) A&S:1:32, Fitter: 3:30, total time was 5:20. I tried setting DEBUG_NOHDMI in mycore.qsf, and the timings changed to A&S: 0:21, Fitter: 1:53, total time was 2:28 To double...

My "daily driver" is a MacBookPro and I have bootcamp on it for games and FPGA development. There are threads from 13 years ago saying that Quartus works under Parallels, but I'm wondering if anybody here has any more recent experience with it? Or more to the point, any other software I'd need for MiSTer FPGA development that would run un...

@Grabulosaure, that all makes sense, thank you! I tried booting the MisTer, waiting for the OSD to show up, and then ran my core (Arcade_Bagman) from the Programmer but it still just produced a black screen, so I'm still doing something wrong. Is there something I have to edit in the core itself (which I understand may vary between cores) in order ...

@Grabuloasure, regarding HDMI - does the core specify video resolution and bit depth, and the ARM/Linux side allocates appropriate memory and gives the FPGA access to said memory (coming out of the gigabyte of shared RAM IIRC?)?

Do most cores just completely "fill" this memory every frame from scratch?

I'm having a hard time finding any documentation on how the MiSTer system is architected, maybe it's buried over in the dead Atari forums? Anyway, I'm happy to contribute to any sort of documentation myself - in particular, a quick start guide for developers (for example, I'm not the only one who didn't notice the "you need to use version 17 o...

Based on http://system16.com/hardware.php?id=766, it does seem like Gauntlet is very similar hardware. The only major difference I can see is the main CPU is running twice as fast as System 1 hardware.

Highly recommended from me as well!!

Well, that didn't work. The resulting boot.rom was about 84k long, placed in the root directory of the SD card, but running that core from the Programmer still produced no output. I googled a bit but couldn't really find any information about the boot.rom format. I did see a bit where you could include a rom with the rbf by inserting a 16 byte head...