MiSTer FPGA Forum

Hi angry Sorgelig, I'm working on my own add-on for MiSTer including SDRAM. Will be published under GPL 3 when finished. I saw the layout of the XSD module with two SDRAM chips. How sensitive is this layout regarding impedance and length of traces and crosstalk? Originally planned on a two layer board, but don't think it will work out. Same applies...