MiSTer FPGA Forum

sonycman

Not an answer to your question, but: Does this mean the game boots when you have it in bin/cue format? Or just that it shows up in WB? It shows up and let me browse it contents, yes, not trying to boot it yet, it needs to setup emulator etc... Might be a CHD bug? It has definitely two data tracks: http://redump.org/disc/3427/ This is what i'am int...

sonycman

Hi there. Recently tried Cannon Fodder (EU).chd image and it even not recognized in workbench 3.1.4 on Mister. The same image converted in .bin/.cue recognized fine! Is that so for everybody? This image consists of two data tracks, and from the mister's main code it seems it mistakingly accesses first track using offsets and track type of second tr...

sonycman

It seems extra device is the slave IDE controller, which is disabled in the options.
Strangely it is responding somehow and appears as Unknown in the toolbox, but cannot be written to or inquired from.

sonycman

Hello!
Using A1200 config with 3.1 kickstart, having workbench 3.1 loaded from .adf.
Primary IDE enabled with .hdf image selected.

And hdtoolbox showing extra scsi device (two in total).

Is this normal, or this is a problem on my side?

sonycman

I`am planning to port NeoGeo core to Zynq Z-Turn board, thus I need to make my own SDRAM addon board.

Haven't you tried to place SDRAM chips on the different layers, one on top, and other on the bottom, one strictly over another?
This way would greatly reduce the length of the tracks.

sonycman

Oh, indeed?
And you are not having any issues with the memory stability between any builds?
Interesting. Thank you, Alexey.

sonycman

To decrease number of pins needed for the SDRAM.
Some kind of optimization.

sonycman

Hi!
Sorry for a silly question - but I just can't find .sdc file in NeoGeo core sources, where constraints for the SDRAM memory must be located.
There is sdram2.sdc file in /rtl/mem folder with constraints for the second SDRAM2 module, but thats it...

Am i missing something?

sonycman

Okay, i see, thank you.

But it seems that no one tried these new chips in practice?

sonycman

No need for more.
Many sdram boards based on 166MHz AS4C32M16SB-6TIN can't go much higher, actually.

sonycman

Hello!

It seems all the 128MB SDRAM boards is made of AS4C32M16SB chips.

But what if we try AS4C32M16SC?
These have even lower operating current - 60ma only, vs 110ma for AS4C32M16SB.
Not sure if they differs in any other way.

Will it be good idea to try?

Regards,
Vlad.

MiSTer FPGA Forum

Search found 11 matches

Re: CHD handling bug?

CHD handling bug?

Re: HDTOOLBOX shows extra scsi device

HDTOOLBOX shows extra scsi device

Re: NeoGeo core: where is main .sdc file?

Re: NeoGeo core: where is main .sdc file?

Re: For the SDRAM add on, why DQMH and DQML connected to A11 and A12?

NeoGeo core: where is main .sdc file?

Re: 128MB SDRAM using AS4C32M16SC chips

Re: 128MB SDRAM using AS4C32M16SC chips

128MB SDRAM using AS4C32M16SC chips