MiSTer FPGA Forum

also just leaving this here: java virtual machine core

only if the fpga (Cyclone V SE) had transceivers, or hard PCIe controllers.

the SX version of Cyclone V has PCIe controllers included, 1 or 2, the sockit version.
from the Cyclone V Overview manual: "The PCIe Gen2 x4 support is PCIe-compatible."

Just a suggestion how the gpu hardware emulation issue should be handled.

just leaving this here: pcie slot expansion to the fpga-side, so that any gpu stuff can be run directly on the gpu, any api, or even use HPS side software apis, vulkan, opengl, on the linux, or some emulated/adapted direct3d, 9/11/12

whats the deal with the template not being for the quartus prime lite 21 version.

edit: I would suggest to update to HLS on Quartus Prime 21.1 (high level language synthesis) to accelerate and make the development/support simpler. Again, the only thing you do after the compilation, you wire the outputs to proper places, like I suggested.

Hackshed_Carl wrote: ↑Sat Jul 23, 2022 9:40 pm Crack on then pal

I'm on it, dev environment set up

dshadoff wrote: ↑Sat Jul 23, 2022 8:36 pm You will learn a lot.

Did I tell you that I'm a semiconductor university master.

I actually suggest that there is a vhdl direct patcher to convert the underlying de10nano design to any other platform, through the wrapper.

nope its easy, no need to make it harder than it is, and also, no making of servants because of pride reasons, thanks whats the diffculty, you literally just take the original fpga wiring, and fit the correct wires. have fun, because I know you want to do it :) and my purpose is to someone, anyone, or even me, just a reminder that this can and shou...

there should be automated wrapper construction for the usual de10nano intel cyclone-v fpga cores, to fit other similar cyclone-v containing evaluation boards, like arrow sockit and de10standard. simply this would be a wrapper for each fpga soc platform, sockit and de10standard, so the normal pins and interfaces are re-routed to the appropriate devi...

btw, someone needs to check the sdr sdram vs ddr3 sdram speed/latency claim, by checking I found that they are practically the same, for the reads, assuming not too much different for writes, both something around 12ns, for sdram and ddr3. arrow sockit might be even better than de10 nano, because it has dedicated 1gb of ddr3 on the fpga side, as we...

just sharing the idea, I have arrow sockit, without the memory enhancement, I will do it, but someone needs to port it to the Mister DE10-nano kit. um, really, if you have the asic parts, you mostly have the JIT implementation, already, the microcode has to be stored and loaded for the local mini core, by the instruction controller unit. its then a...

unfortunately it is, because none of the major players, intel, amd, even you, in here, are using it, change my mind, even if the idea was floating around, you did not heed to it, let me re-phrase: you can have all instructions implemented in one fixed size silicon logic block, instead of giant silicon logic footprint. this applies to both asic and ...

if someone has interest, they could do the emulation of x86 processors, even current, by dynamic re-wiring of instructions, for every instruction, just-in-time, not asic instruction/ALU blocks, in the fpga, thats dynamically switching the structure of the core, or cores, whenever some new instruction is given by the program counter/unit. idea is to...

also, 256MB sdr sdram chips are around under ten usd

i hope the main project will work directly on the SoCKit

that it seems like to be, that 80usd is with vat

sockit dev-kit is around 80usd, from arrow, i guess the de-10 standard could be mass ordered to be the same price.

for the hsmc equipped boards, there should be ready made SDR SDRAM boards, even stuff like DDR4 boards, off-the-shelf.

Getting rid of the two boards and make it compatible with de10-standard and SoCKit dev-kit.

you could have a power manager in the LTC connector
https://www.analog.com/en/products/ltc2 ... t-overview
https://www.analog.com/en/products/ltc2 ... t-overview

You only need time when dealing with "the world".

You can have it powered always.

So it is the same as a computer that has its battery empty, asking for time, all the time, you could manually input the time too.

What if you sleep the board, DE10, with either from battery or wall power, would it hold the time?

could you partition memory usage, that some part will be on any sdr sdram and slower stuff is on the ddr3 sdram, shared or dedicated

they are actually not expensive, also all-in-one de10-standard, including 64MB SDRAM. there is usb-otg, you can external hub it, if you need to. its actually half the price, and the new one is about the same combined as the add-on parts together. the ultimate replication board would be the DE10-Pro, 2.8M logic, 32GB DDR4 RAM If you like linux, reco...

if the hps can have time, by linux, why cant you just ask the linux to provide the time, you can set it to whatever 1999 you want

edit: set the fpga to a certain speed, then make your own clock

Have you inspected the possibility of running the stack on other boards?

At least those that have the same FPGA soc, cyclone V with arm, like the SocKit, but it has 1GB SDRAM on the FPGA.

https://www.terasic.com.tw/cgi-bin/page ... 6&PartNo=2