MiSTer FPGA Forum

Ok thank you! So my question 2 is completely solved and the table above is right.

Additional investigations: 2) I have used Intel schematic (https://software.intel.com/content/dam/develop/external/us/en/documents/de10-nano-schematic-849456.pdf), plus some TCL files in the MemTest utility - I have no idea of the language used, but it is readable (https://github.com/MiSTer-devel/MemTest_MiSTer/blob/master/sys/sys.tcl & https:/...

Partial answers by myself, still welcome any feedback confirming or correcting me, thank you! 1) For XSD 2.5, it seems I can solder U1A and leave U1B and U3 unpopulated. As well it seems I can either use 256MBIT or 512MBIT parts (so yes, I could create a 32+32MB module using XSD 2.5 saving 15-20€ compared to a 128MB option). What can not be done is...

Hello all I want to do a couple of SDRAM HW modules myself (I already have some soldering experience with my own PCBs), and I have a number of questions looking at the schematics and information of the three available designs (I used the link https://github.com/MiSTer-devel/Main_MiSTer/wiki/SDRAM-Board-Assembly-(DIY) ) , if anyone can throw some li...