The A2FPGA project has some working Verilog code for IIgs functionality that might be of interest to folks working on this:
Feel free to PM about it. Happy to collaborate in adapting it for use in a Mister IIgs core.
The A2FPGA project has some working Verilog code for IIgs functionality that might be of interest to folks working on this:
Feel free to PM about it. Happy to collaborate in adapting it for use in a Mister IIgs core.