The idea is to have a single core compiled with different SDRAM clock shift settings. Although indeed, the exact delay up to the pin is not well controlled (right now), as a relative measurement, this is reliable. I have made a collection of MRA and RBF files. Each one delays the SDRAM clock by 250ps with respect to the previous one. If you start at a middle value, like 5ns (=5000ps), it should work. As you approach lower and lower delays, it will eventually fail. So will it fail too if you move towards larger delays. The wider the range you get, the better.
These are the values I get for the modules I have.
Code: Select all
Module | Min | Max | Remarks
-------|------|-------|---------
1 | 3.5 | 8.25 |
2 | 2.5 | 8.5 | 32MB
3 | 2.5 | 8.75 | 32MB
4 | 3.0 | 8.0 | 10uF added
7 | 4.0 | 8.25 | min improved to 3.5ns by adding 33uF
8 | 3.5 | 8.0 |
9 | 3.25 | 8.25 |
Module description
ID | Part No | Units | Size
----|------------------|-------|-----
1 | AS4C32M16SB-6T1N | 2 | 128
2 | W9825G6KH-6 | 1 | 32
3 | AS4C16M16SA-6TCN | 1 | 32
4 | AS4C32M16SB-7TCN | 2 | 128
5 | W9825G6KH-6 | 1 | 32
6 | AS4C32M8SA -7TCN | 2 | 64
7 | AS4C32M8SA -7TCN | 4 | 128
8,9 | AS4C32M16SB-6T1N | 2 | 128
Please find the files attached. Just unzip them to your MiSTer root folder. This is mainly intended for module builders, but anyone can test their modules at home and check how they do against the ones listed here.
Note that these RBF files only produce analogue video. No HDMI output at all.
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