Memory Latency

[Centurion030]

My main question regarding the sharing of the DDR3 memory between the FPGA and the ARM is this: at what point would a simulated CPU show latency issues? For example, the TMS9900 used in the 99/4A, was 3.3 MHz. There is an expanded memory option that boosted its memory to 1MB and there were GRAM devices too. All of which would exceed the on-board block RAM of the FPGA.

I have read it is possible to set aside an amount of the DDR3 while reducing the total for the ARM -- say a 64Mb chunk for the FPGA. At what point could one expect memory latency issues with the FPGA using the DDR3?

The original 99/4A actually had four wait states implemented as the 16-bit data bus was converted into an 8-bit one. So, it was not really running as fast as it could. The only onboard RAM was a 128 x 16 byte static RAM.

Respectfully,

James

[Sorgelig]

For low latency RAM there is SDRAM module.