Learning to develop a new MiSTer core

[TechCowboy]

I want to learn more about developing a MiSTer core. What would be the simplest core to review the source of?

[sajattack]

This thread should probably be under "Development For MiSTer", also check this out https://www.youtube.com/watch?v=eyb_ONDubcU

[RndMnkIII]

I've checked MiSTer Template project but seems too basic, because don't show how to work with rom loading into SDRAM or how to access to SDRAM data from a core.

[Sorgelig]

in this case you have to look into some console/computer core
Using SDRAM is quite complex to be a "simplest" core.

[AmigoMexicano]

Also interested on this.. I want to make a core for the arcade "Phelios" and have no idea where to start. I come from PHP web programming...

[dshadoff]

The best place to start depends on what you already know.
- Introductory Verilog/VHDL book, and some digital electronics (something like Arduino-level) is a basic place to start before trying to understand any code.

As for the code, pick a simple existing core like an OLD arcade game or one of the earliest computers (think: simple !), and study the Git commit log.
Once you understand how people added to the core, you can start to see how things are put together within the core.

The framework is another level...

[R4mbo]

Same here I enrolled in the nand2tetris course:
https://www.nand2tetris.org/ (actually the coursera edition)
to close some gaps and get better understanding of the hardware.
I'm almost finished with Part I (the Hardware-Part).

Next step for me would be to create a template Project, meaning very general but with most possible functions built-in but commented-out.
Thanks for that YT link @sajattack.

[sajattack]

Same here I enrolled in the nand2tetris course:
https://www.nand2tetris.org/ (actually the coursera edition)
to close some gaps and get better understanding of the hardware.
I'm almost finished with Part I (the Hardware-Part).

Next step for me would be to create a template Project, meaning very general but with most possible functions built-in but commented-out.
Thanks for that YT link @sajattack.

I'm not sure if you've seen it, but I implemented Nand2Tetris for MiSTer https://github.com/sajattack/Hack_MiSTer

[matt]

Nand2Tetris is a great course. I've completed all the coursework for the first of two classes. I'd highly recommend it for someone wanting to dip their toes in the water. You learn a toy description language, but it's a good first step depending on your learning style.

[R4mbo]

Same here I enrolled in the nand2tetris course:
https://www.nand2tetris.org/ (actually the coursera edition)
to close some gaps and get better understanding of the hardware.
I'm almost finished with Part I (the Hardware-Part).

Next step for me would be to create a template Project, meaning very general but with most possible functions built-in but commented-out.
Thanks for that YT link @sajattack.

I'm not sure if you've seen it, but I implemented Nand2Tetris for MiSTer https://github.com/sajattack/Hack_MiSTer

Thats great! Good to know. When I'm finished with the course this will get helpful I think.

[moscow]

For somebody who is completely new to VHDL / Verilig it might be good idea to consider trying with smaller board. One of the examples is https://maximator-fpga.org. It's small but nice thing. You can use Arduino shields with it, and it offers 3.3<->5V converter.
Maybe it's just easier to learn on something simplier, synthesis process runs faster (especially on Quartus Lite), and even if you break something it's bit cheaper than DE-10 Nano.

BTW. Currently there is a problem with downloading Quartus Prime from intels' pages. There is a related topic on the forum
https://forums.intel.com/s/question/0D5 ... uage=en_US
I've posted direct links there allowing to download Quartus Prime Light in various versions from 13 to 19 (right now it's last but one post in this thread).

If remember corretly - most of the cores are now build with v16.0 or 16.1 (and 13.0 for MIST)

[macro]

I started with adding a game to an existing core (Devil Fish on galaxian core), then added quite a few bits of extra hardware to a console core to allow it to handle the arcade versions that run on it (Astrocade) and I am now writing my own core (nearly) from scratch for another arcade game (Crazy Balloon) - well, other than using Z80 code and re-purposing the video timing code from Pacman, although I did make it match the real hardware - it uses Z80 cpu, character graphics, sprite (yes, one sprite), memory mapping and IO ports - so once done I should be familiar with enough to embark on the next (bigger multi CPU) project

I always find the best thing to help you learn is to pick something that you are interested in, that seems manageable (i.e. don't start with a multi CPU based system for your first project) and go from there.

There are people on here that will answer your stupid questions (well, they answered mine!) to help.

[R4mbo]

I'm not sure if you've seen it, but I implemented Nand2Tetris for MiSTer https://github.com/sajattack/Hack_MiSTer

I just cloned it and tried to compile in Quartus Prime Lite 17.
But I instantly get following error:
Error (23018): Tcl Script File sys/build_id.tcl not found

Might be some basic stuff, but I'm new to FPGA's and the Software.
Can you give me a hint how to compile?

[moscow]

[...]
I just cloned it and tried to compile in Quartus Prime Lite 17.
But I instantly get following error:
Error (23018): Tcl Script File sys/build_id.tcl not found

Might be some basic stuff, but I'm new to FPGA's and the Software.
Can you give me a hint how to compile?

It looks like conf management file. Not sure if this is cleanest solution, but I took this file from another project e.g.
https://raw.githubusercontent.com/MiSTe ... ild_id.tcl
... and it worked (at least I got .sof file in the output_files dir

[sajattack]

Sorry, my git was ignoring that file. Fixed. You'll want to set it up to generate an rbf, not a sof.

[nullobject]

I want to learn more about developing a MiSTer core. What would be the simplest core to review the source of?

To build a core, first you should get a handle on some of the fundamentals (depending on your skill level). If you're completely new to FPGA development, start by blinking LEDs on/off, etc. A good book on VHDL and/or Verilog is highly recommended.

In the early phase, I would also suggest completely doing away with the MiSTer framework — it will just complicate things. You really want to keep your compile-time as low as possible, so that you can iterate quickly and learn fast.

This means that you will need an IO board and a PVM, because you won't have HDMI output without the MiSTer framework (it just adds extra time to the compilation process). Once your core is progressing, then it makes sense to integrate it with the MiSTer framework and get everything working nicely.

I have some sample projects I wrote to get started on the DE10-Nano: https://github.com/nullobject/de10-nano-examples/

Some of these components I built to test things in isolation while I was working on Rygar (i.e. video, tilemaps, sprites, sound, etc.)

If your skills are more advanced, then I suggest spending time studying how other cores work.

I spent a lot of time making sure that the Rygar source code is well structured, for future me, and for others: https://github.com/MiSTer-devel/Arcade-Rygar_MiSTer/

[nullobject]

I can also recommend this book, which is a fairly gentle intro to arcade hardware in Verilog. It covers fundamental things like CPU, memory, video hardware, tilemaps, sprites, etc.

You can run their example code in your browser, which is nice for playing around with the concepts they cover.

51JOCwN0IoL.jpg (41.91 KiB) Viewed 9621 times

[R4mbo]

It looks like conf management file. Not sure if this is cleanest solution, but I took this file from another project e.g.
https://raw.githubusercontent.com/MiSTe ... ild_id.tcl
... and it worked (at least I got .sof file in the output_files dir

Thanks

[puu]

Please tell me how to use the clock information that Linux has on the FPGA side.
I thought I should use RTC [64: 0] of hps_io, but the contents remain 14004700101000003 and it doesn't change. I think it means 1970/01/01 00:00:03.
It is connected to ethernet, and when you type the date command from terminal, the correct current time is returned. Is there a command or something to update the RTC in hps_io?

[Sorgelig]

RTC updated only ONCE when core starts. If your MiSTer has RTC board, then your core will get RTC at start in any case. If your MiSTer has no RTC board, then you have to connect to internet in advance to let the linux update the time. In Menu core you will see the time when when it will be available. Then you can launch the core. If you launch the core through USB blaster (from Quartus) and you have no RTC board then your core won't get RTC because linux reboots once it detect USB blaster loading.

[puu]

Thank you for teaching. Since it was debugged by booting from USB blaster, it was 1/1 in 1970 every time. I understood the cause.

[R4mbo]

It looks like conf management file. Not sure if this is cleanest solution, but I took this file from another project e.g.
https://raw.githubusercontent.com/MiSTe ... ild_id.tcl
... and it worked (at least I got .sof file in the output_files dir

I made myself familiar now with all the files and folders a MiSTer Project has.
[sys] contains the Framework and should not be modified. I found out it should be updated by copying it from the Template-Project: https://github.com/MiSTer-devel/Template_MiSTer
After doing so, I was able to compile the Hack-Core into a beautiful .rbf File and use it on my MiSTer.

[SerErris]

Ignor me ... found the other thread on book recommendations.

[SerErris]

I can also recommend this book, which is a fairly gentle intro to arcade hardware in Verilog. It covers fundamental things like CPU, memory, video hardware, tilemaps, sprites, etc.

You can run their example code in your browser, which is nice for playing around with the concepts they cover.

@nullobject, as this is Verilog and also the top Level of any Mister project is a Verilog .sv file ... do you think it is better to start with Verilog or with VHDL?

I started now on VHDL and put nearly all the implementation of nand2tetris into VHDL code, which works for now in simulation. However to implement it into Mister with sdram and video output (and rom) I need to understand the structure. That is in any project, even in the template Verilog and hard for me to digest right now.

I even fail to understand how to integrate my code in there on the simplest things.

I also found that the cores are mostly not commented at all about anything for someone to understand what the codeblocks are for or what they are actually doing.

Looking at any other core (e.g. the simplest arcade cores) still does not deliver any answer. I am not even able to identify how the main system clock is generated on the C64 core.

I believe, we need to get some more documentation for beginners to get it going. None of the cores I looked at are currently good for learning as they do not even contain any comments in the code.

No comments also means that no one could help to debug easily ...

Is this just me?

[nullobject]

@nullobject, as this is Verilog and also the top Level of any Mister project is a Verilog .sv file ... do you think it is better to start with Verilog or with VHDL?

I think you need to at least be familiar with Verilog/SystemVerilog and VHDL — but you only need to be proficient in one of these. It doesn't really matter which one. I find VHDL much nicer to work with, and I appreciate its strict type system. But at the end of the day, it's just a matter of taste.

If you are working with the MiSTer framework you will definitely have to deal with at least some Verilog/SystemVerilog. For example, as you mentioned the entry-point into your core is the "emu" module, which is written in SV. But the rest of your core could all be written in VHDL, for example (this is the case for me).

Also, if you want to use any 3rd-party modules (CPU, sound, etc.), then you will have to be able to integrate them with your project. They may not be written in your HDL of choice.

Some developers have put a lot of care into making it easier for people to integrate their modules. I know jotego's sound libraries provide both Verilog and VHDL options for the top-level module, which is awesome.

I believe, we need to get some more documentation for beginners to get it going. None of the cores I looked at are currently good for learning as they do not even contain any comments in the code.

No comments also means that no one could help to debug easily ...

Is this just me?

Coming from the software world, I find the lack of care that people put into their HDL code a bit crazy. But that is the nature of open-source — sometimes people don't have time, get bored, or move on.

I suggest submitting PRs to projects if you want to clean something up, add comments, or write a bit of documentation. I'm sure it would be welcome, and it benefits everybody.

I also agree that there is very little in the way of documentation for beginners wanting to get started writing cores in MiSTer. Most of this stuff is just kept in people's heads.

I think we all need to work on improving the developer documentation in the MiSTer wiki.

[dshadoff]

There are a lot of shorthands that you aren't likely to get people to change (as in: they are conventions that you'll need to learn), and yet there are lots of things which could make the code easier to understand. (But I frequently have similar comments about other peoples' software as well...)

One item that really doesn't cost anybody anything, would be to name things clearly....
1) If RESET is active low, it should be named RESET_N, or at least commented at the interface portion at the top of the file
2) Super-short variable names are not helpful to anybody. 'V' can be 'video', 'vertical', 'volume', or may simply be the next variable after 'U'...

There are also inevitably going to be some complex-looking logic AND/OR/etc. expressions at points in the code, which are going to be unclear at first glance what they accomplish. Placing a small comment next to these would be incredibly helpful for the next person.

[SerErris]

Thanks @nullobject, really appreciated.

I am beginning my way into all of that hardware world and started a hack computer with VHDL, now trying to run it on Mister.

Now I am struggeling if I should now do everything again in Verilog. I have a hard time to understand anything in any of the cores that are implementing a simple vga screen as that section is in Verilog and it is very hard to read.

Verilog reminds me on pearl. You can do very short code, that no one else can read anymore. So currently I like VHDL more because it is much better to read and understand for a beginner like me.

I even had a hard time to understand when a new module is loaded and where it is defined, before I understood that you just call it in Verilog and dont specify it before.

So I believe that is quite typical for a beginner in hardware design but it is so confusing.

[Sorgelig]

Verilog is pretty close to C.
If you are long time C developer, then with a little HDL introduction you should be able to read Verilog. Pretty much 1:1 with some adjustments to HDL specifics.

Same VHDL is basically Pascal for HDL. If you plan to write in VHDL, then try not to change variable cases, as VHDL being very strict language completely ignores the variable case making sometimes hard to read. Some developers like to write in a single module RESET, reset, Reset. This is hard to read. Many text editors with auto highlighting of the same word don't work with mixed cases.