Hi all
I'm the recent owner of a DE10 Nano board, and even though I'm an IT guy I have no clues about low-level circuits/chips design, let alone how to implement them using an FPGA... So I'm trying to learn something new, here.
Question for the pros: I've been wondering how an FPGA like the Cyclone - with 110k logic elements - can replicate chips like a 486sx, which was made of over 1M transistor if I recall that correctly.
Since such a core does exist (ao486) I guess the number of logic elements doesn't directly relate (1:1) to the number of transistors in a CPU/chip, but I'm still very curious to learn how that works
Any pointers for me please?
Thanks in advance!
Limits of the DE10 Nano board?
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redsteakraw
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Re: Limits of the DE10 Nano board?
I found this reddit thread I hope this helps
https://www.reddit.com/r/fpgagaming/com ... _elements/
https://www.reddit.com/r/fpgagaming/com ... _elements/
Fear is the mind killer!
Re: Limits of the DE10 Nano board?
One thing to keep in mind is that modern FPGAs are not just a bunch of logic; they also have dedicated "hard blocks" for specific functions that would be especially inefficient or incur a major performance penalty if implemented in generic logic. Examples of these include blocks for RAM, MAC (multiply-accumulate) and SERDES (serialization/deserialization; think SATA, PCIe, Ethernet, HDMI, etc.).
For example, on-chip RAM is often included in CPU and GPU transistor counts. A conventional SRAM bit is 6 transistors and a 486SX has 64 Kbit of L1 cache, so of those roughly 1 million transistors about a third might be accounted for by the cache (depending on the specific memory architecture Intel used). As a point of comparison, 64 Kbit also happens to be the amount of block RAM in the "1K" iCE40 FPGAs, which are quite small by FPGA standards.
For example, on-chip RAM is often included in CPU and GPU transistor counts. A conventional SRAM bit is 6 transistors and a 486SX has 64 Kbit of L1 cache, so of those roughly 1 million transistors about a third might be accounted for by the cache (depending on the specific memory architecture Intel used). As a point of comparison, 64 Kbit also happens to be the amount of block RAM in the "1K" iCE40 FPGAs, which are quite small by FPGA standards.
Re: Limits of the DE10 Nano board?
I'd have never thought of the cache being included in the CPU transistor count (duh) but of course it fully makes sense.
Thus the logic elements of an FPGA are not created equal, I infer: there are simpler and more complex elements in play - within that logic elements pool - thus the total number of achievable "CPU transistors" scales much higher than the simple count of logic elements..
Thanks for the explanation
Thus the logic elements of an FPGA are not created equal, I infer: there are simpler and more complex elements in play - within that logic elements pool - thus the total number of achievable "CPU transistors" scales much higher than the simple count of logic elements..
Thanks for the explanation