Possibility for DDR1-RAM boards in the future?

[H6rdc0re]

Would using DDR1 RAM for next generation RAM expansion boards be the next step? It will double the bandwidth, offer higher clockspeeds, DDR1 RAM can be found with bigger sizes per RAM chip and most important of all still allow for low timings (2.2.2.5 1T) up to 200MHz or 400MHz effective. Finding DDR1 400MHz with 2.2.2.5 1T timings will be difficult but 266MHz or even 333MHz should not be and it should allow for 256MB boards. Just a thought.

[andrezheng]

The IOs in the expansion headers are 3.3V LVTTL. Not compatible to the DDR voltage level.

[grizzly]

Voltage levels can be adjusted with components sure it will cost more but it CAN be done.
The downside of adding components to adjust voltage on the same board/near memory chips/traces can be interference that will probably lead to a lower usable speed.

Then not to forget the connector on the de-10 that is one BIG problem with achieving higher speeds.
Will DDR1 be easier/harder/the same then SDRAM to get in trouble with the connector?
My gut (and a wild guess based on pretty much nothing) is DDR1 will have more trouble with the connector.
So all in all with DDR1 when used on the de-10 will the speed then be any higher or even lower???

[Sorgelig]

Adding level shifters is not an option for such small size of board.
There is also limit of max frequency on that type of connector. You can't go over ~150MHz, so advantages of DDR won't be used. DDR also have higher latency than SDR which will further limit its usability.
So, it's unlikely DDR module will appear for MiSTer.

[H6rdc0re]

Adding level shifters is not an option for such small size of board.
There is also limit of max frequency on that type of connector. You can't go over ~150MHz, so advantages of DDR won't be used. DDR also have higher latency than SDR which will further limit its usability.
So, it's unlikely DDR module will appear for MiSTer.

So running DDR1 266MHz should be possible then as it's running at only 133MHz. Running at these low frequencies it should always be able to run at the lowest latencies (CAS 2.0, tRCD 2, tRP 2, tRAS 2 and 1T command rate) similar or lower than SDRAM. It would also double the bandwidth. The most important reason I brought this up is because DDR1 was made with higher density chips allowing for bigger RAM expansion boards and general availability. The higher bandwidth and low latencies are just bonusses.

Just a thought future proofing Mister

[Sorgelig]

DDR requires more precise signal matching and this will be a problem. It also requires more pins. Even with SDR there are problems to make it work on high clock. Actually double rate is only for DQ signals. All other signals use the same single clock rate.
As for capacity, none of cores (but one) use more than 64MB. Only several games in NeoGeo require more than 64MB.
I think 128MB will cover all systems possible to simulate on MiSTer. Bottleneck is not size but random access time where DDR won't be better than SDR.

[throAU]

To elaborate on the above discussion - as I understand it SDRAM on the expansion is used as its the lower latency "modern" memory available. The DE10-nano board already has 1GB of DDR3 on it which would have more bandwidth (if bandwidth was the problem), but the latency is worse.

Bandwidth isn't the problem, latency (for the types of cores mister currently emulates) is.

Modern platforms have big caches, buffers, etc and don't rely on precise timings as the components in them all run asynchronously, but the old school platforms are all about precise timings between components.