How do Genesis core download ROM to SDRAM?

[mindstation]

Hello!
I'm trying to port MiSTER Genesis core to DE2-115 board. The only board I have.

The dufficult thing for me is ROM copying to SDRAM.
In the emu module (sys_top/emu) I see ROM data write to port zero of sdram module.

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str 735: .din0({ioctl_data[7:0],ioctl_data[15:8]}),
str 737, 738: .wrl0(1), .wrh0(1),

There and below str is a string number in the correspond module.

Where ioctl_data is 16-bit bus:

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str 324: wire [15:0] ioctl_data;

It's connect "ioctl_dout" of sys_top/emu/hps_io with sdram.

It's mean data is coping word by word (16 bits). Right?

But in hps_io module (sys_top/emu/hps_io) size of "ioctl_dout" depends of "WIDE" parameter.

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str 111: output reg [DW:0] ioctl_dout,

Where DW is 7 if WIDE is 0.

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str 166: localparam DW = (WIDE) ? 15 : 7;

And "WIDE" is 0 in the hps_io.

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str 28: module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)

Therefore "ioctl_dout" is only one byte sized, and one byte comes from ARM by "io_din" too.

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str 642: ioctl_dout <= io_din[DW:0];

"ioctl_data[15:8]" is undefined in this case.

Where am I wrong?

[Sorgelig]

you need to look into module instantiation parameters, not default ones.

[robinsonb5]

Nice project - have fun with it!

What are you planning to use instead of the de10-nano's HPS stuff?

[mindstation]

you need to look into module instantiation parameters, not default ones.

Thank you!
WIDE is 1 in sys_top/emu. Why didn't I see it?

What are you planning to use instead of the de10-nano's HPS stuff?

I want to get just a Genesis core on DE2-115 without OSD and special features.
Maybe, a special controller with registers available to CPU M68K of the core will be added in the project.

Now I know WIDE is 1, and I have another question.
Question about "ioctl_addr".

At ROM loading the "ioctl_addr" is incremented by 2 if WIDE is 1 (sys_top/emu/hps_io):

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641: ioctl_addr <= addr;
644: addr <= addr + (WIDE ? 2'd2 : 2'd1);

According MT48LC64M (Micron SDRAM) datasheet every column address selects one word (16-bit) for the 16-bit SDRAM version.
Therefore when "addr" are incremented by 2, every odd column/word will be skipped in SDRAM. It's right?

Do the Genesis core skip odd words when reading SDRAM?

[mindstation]

I made a controller is copying ROM image from Flash memory of DE2-115 to SDRAM.

If I make increment ioctl_addr equals 2, then I have odd words skipped in the SDRAM.

The "FEFE" pattern was loaded to all cells of SDRAM before Genesis core loading to FPGA.
The core is modified for DE2-115 board: top level entity ports reconnected to actual pins, the status register has hardcoded state, SVP is disabled.

The core reads stack and program entry pointers correctly (picture below) when ioctl_addr increment equals 1.

The ROM is "Streets of Rage (W) (REV01) [!].bin", start bytes is:

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00 ff ff 00 00 00 02 08  00 00 02 00 00 00 02 00

Why do Genesis MiSTER ioctl_addr increment equals 2 at ROM loading?

DE2-115 has ISSI IS42S16320D-7TL SDRAM chips.
The SDRAM datasheet and DE2-115 schematic can be viewed here:

https://disk.yandex.ru/d/pgiUVq4hL8aD7A?w=1

[paulbnl]

If you just look at the sdram module instantiation then you can see that it doesn't use bit 0 of ioctl_addr because ioctl_addr is a byte address and it is writing words.

[mindstation]

It's clear now. Thank you paulbnl!