Some Thoughts From the Terasic Team

[Hazel W]

I work for Terasic (to validate this, my office TEL is +886-3-575-0880 #218) and would like to share some thoughts from our sales & support team.

First is we really appreciate the MiSTer project and users for realizing DE10-Nano's potential. But at the same time we have to admit we've received many reports of DE10-Nano damage that are linked to MiSTer recently, that it's becoming a bit overwhelming.

I'm sure most of the users are seasoned MiSTer hobbyists and know how to protect their hardware well. But for someone who's totally new to FPGA or MiSTer, I hope she/he may spare some time to read the notes attached http://mail.terasic.com.tw/~tien/202106 ... _Users.pdf, before connecting his/her DE10-Nano to any new device (On the other hand if the newly-arrived kit is found defected, pls don't wait until the warranty is expired—just contact us ASAP. We will be happy to take care of the problem for the user!)

My apologies if my English doesn't sound natural as it's not my 1st language. If you have any feedback pls feel most welcomed to reach out to the Terasic team or leave comments to me.

[Xbytez]

As the link provided seems to take a long time to download I have also attached the PDF you linked to in this post.

Notes_for_DE10-Nano_Users.pdf

(712.52 KiB) Downloaded 784 times

[pgimeno]

Here is a transcript, to allow copy/paste and searchability:

Terasic Inc.
TEL: 886-3-5750880
FAX: 886-3-5726690
9F, No. 176, Sec. 2, Gongdao 5th Rd.
HsinChu City
Taiwan, R.O.C. 30070

Notes for DE10-Nano Users

As the manufacturer of DE10-Nano, we noticed in many MiSTer projects, the SDRAM daughter card and I/O board the users choose to connect DE10-Nano with are either homemade or supplied by other brands, therefore the quality varies. Unfortunately, sometimes incompatibility issue does arise when the timing closure becomes marginal. In other cases, irreversible damage on the FPGA I/O of DE10-Nano was found resulting from mishandling.

If you are planning to buy or make your own SDRAM or I/O daughter card for the MiSTer FPGA project, we highly recommend you to read the following first.

1. Before connect your DE10-Nano to any daughter card, please first follow \DE10-Nano_v.x.x.x_HWrevC_SystemCD\Manual\Getting_Started_Guide.pdf to make sure the HPS side and the FPGA hardware of the main board are fully functional. Only then are you ready to test your MiSTer project.
   If any part of the hardware is not functional during the initial test, please email Terasic support staff at support terasic.com immediately and do NOT proceed to test the MiSTer project.
2. There are no notches/dents on 40pin connectors, so pay attention how you plug the daughter boards!
   It's also easy to plug it backward or shifted - this may damage DE10-nano board upon power up. Make sure PIN1 on one board is matched to PIN1 on other board before the DE10-Nano board is turned on.
3. Do NOT plug in or out the SDRAM or I/O daughter card while the power is still on.
4. Avoid letting any metallic object come in contact with the DE10-Nano board, SDRAM or I/O daughter cards while they are in use. Electric charge could lead to short circuit and damage the hardware permanently.
5. Before starting your own project, read the MiSTer FPGA project instruction provided on github (https://github.com/MiSTer-devel/Hardware_MiSTer)

Important notice: Before implementing your MiSTer project on DE10-Nano, please run the official user-acceptance testing provided by Terasic on the hardware. If you have any concern or question toward the quality of the kit received, please contact us immediately. We will consider the user has approved the quality of DE10-Nano once a homemade or other third-party daughter card is connected to the main board.