Where's the Speccy love?

[ron]

This capture belongs to benitoss's port.

ron_mister_zxnext_benitoss.jpg (85.83 KiB) Viewed 16106 times

[ron]

Here some more pics from Benitoss port

benitoss_mister_zxnextboot01.jpg (95.15 KiB) Viewed 16103 times

benitoss_mister_zxnextboot02.jpg (89.67 KiB) Viewed 16103 times

[benitoss]

As you can see in the pictures the core can read the VHD image and load the firmware of the TBLue and several files of the VHD image file.
Now I am working in the memory part, the idea is similar than the Spectum core. The initial memory logic is done as a dual port but everything goes to the SRAM. So, we need to put the vram memory (16 Kb block X 6 bocks consecutively, 3 blocks for layer2 and another 3 blocks for shadow layer2) in total 96 Kb in the BRAM cache. The problem is that the LAyer 2 has not the same start address (it is not always in the same block of the memory, can be selected by the user through the NextOS. So I can know what is the offset of this Layer2 and apply it to read and write in the BRAM memory
All writes and reads in VRAM we send to this BRAM. The rest of the memory addresses will be handled in the SDRAM.

[NML32]

It's nice to see progress is being made with the ZX Spectrum Next core.

[rampa]

I have the source ported to MiSTer but the SDRAM is not working. Maybe someone could help.

do you have it posted anywhere? Thanks!

[rickdangerous]

No, just shared with some known devs.

[Sorgelig]

As you can see in the pictures the core can read the VHD image and load the firmware of the TBLue and several files of the VHD image file.
Now I am working in the memory part, the idea is similar than the Spectum core. The initial memory logic is done as a dual port but everything goes to the SRAM. So, we need to put the vram memory (16 Kb block X 6 bocks consecutively, 3 blocks for layer2 and another 3 blocks for shadow layer2) in total 96 Kb in the BRAM cache. The problem is that the LAyer 2 has not the same start address (it is not always in the same block of the memory, can be selected by the user through the NextOS. So I can know what is the offset of this Layer2 and apply it to read and write in the BRAM memory
All writes and reads in VRAM we send to this BRAM. The rest of the memory addresses will be handled in the SDRAM.

Where i can read technical info about Next video modes? I need to know which video modes are supported and where video frame buffers can be.

[Ip75]

This looks like the place: https://wiki.specnext.dev

[benitoss]

Every day I am closer

photo_2020-06-08_11-34-31.jpg (79.66 KiB) Viewed 16002 times

photo_2020-06-08_11-31-23.jpg (88.45 KiB) Viewed 16002 times

photo_2020-06-08_11-31-19.jpg (92.07 KiB) Viewed 16002 times

Step by step

[Fallon]

Keep going! ZX Spectrum Next has a fantastic community with plenty of new games and software.

[NightShadowPT]

I'm really excited about this one.

Looking forward to see the result!

Cheers

[benitoss]

Where i can read technical info about Next video modes? I need to know which video modes are supported and where video frame buffers can be.

You have a lot of information in the ZX Spectrum Next Wiki.
Here https://wiki.specnext.dev/Memory_map you have the map memory

The layer2 and shadow layer2 spend continuous 3 banks of 16KB each (in total 6 continuous banks ) . But the position is variable.
NextZXOS moves the Layer 2 bank assignments. Therefore, Layer 2, after NextZXOS boots, is mapped to 16k-banks 9-11. The Layer 2 shadow memory is also assigned to 16k-banks 9-11.
layer2_active_bank -> std_logic_vector(6 downto 0) is the starting 16K bank
The default value of layer2_active_bank is 8 --> "0001000" (minimum value) and the maximum value of this variable is 106 --> ‭"1101010‬"
The default value of layer2_shadow_bank is 11 --> "0001011"
Be carefull although the bank number of default layer2 is 8, it start after the bank 0 start in $040000 so we have to add that ofsset.
it is shown in this line (we add +1 to add the offset of $40000) -->

Code: Select all

layer2_bank_eff <= (('0' & layer2_active_bank_q(6 downto 4)) + 1) & layer2_active_bank_q(3 downto 0); 

layer2_bank_eff is the bank effective abd it is used to calculate the absolute address layer2_addr_eff

Code: Select all

layer2_addr_eff <= (layer2_bank_eff + ("00000" & layer2_addr(16 downto 14))) & layer2_addr(13 downto 0);

So theoretically we have to create a VRAM containing the 6 blocks X 16 Kb of Layer2 banks and Layer2 Shadow banks.

My actual core is running in a Cyclone V 22K cells using SRAM

So, I gonna use the same SDRAM instanciate of your Spectrum core but I have to solve the logical part of the VRAM with variable address.

For me the VRAM will have 96Kb and
1) I will read in it when the core accesses to port B(layer2), but I have to send to the VRAM memory the relative address memory of the layer2 (my starting reference address is always 0) instead the absolute value of the complete address total RAM.
2) To read/write in CPU the core uses port A. The data will be send to the SDRAM unless the part A writes in VRAM (see the next case)
3) To write in VRAM (the core uses the port A), I have to use logic to know if the memory address to write belongs to the VRAM (layer2 or layer2 shadow bloks) or is the rest of the complete RAM. If it belongs to VRAM , I have to convert the absolute address in relative to VRAM and write in VRAM and SDRAM at the same time. If the memory address belongs to the rest of the RAM memory I have to write only the absolute address in the SDRAM only.
Do you think I am right?

Solving this part I think I have the core done, I am really close, maybe I am gonna need your help in the this part.
Thanks

[KnC]

Looking forward to seeing this core make it to the MiSTer
I have been using a emulator for a while now for zxnext hoping for them to become available on the site but having it on the mister would be so much better

[Sorgelig]

if some app/game will change layer 2 position very fast, then you won't have time to re-load layer2 into BRAM.
256x192 is standard Spectrum dot clock 7MHz. SDRAM is 16bit, so every word will be fetched at 3.5MHz. If you will use 2-word burst then fetch will be every 1.75MHz. This is pretty much comfortable access time for SDRAM working at around 112MHz. So you don't need to use VRAM. You can fetch layer2 directly from SDRAM.

there is another strategy for MiSTer: use DDR3 for layer2. DDR3 should be write only from CPU. Write access to DDR3 is usually immediate as you don't have to wait for data. The video system will fetch the video data sequentially, so you can add burst mode to fetch for example a whole line to BRAM buffer and while it renders the line from BRAM to screen, you can prefetch another line from DDR3 to second BRAM buffer.

So, there are several ways to handle the video buffer.

[antonie]

@benitoss, purely out of curiosity, how do you intend dealing with the specnext wifi module and accelerated functions provided by the Pi? E.g. dot commands that are used to load .TZX files. Similarly, NextSync uses the wifi module to send and receive files to/from the outside world.

[Sorgelig]

Need to see what communication channel is used for RPi. If it's UART then MiSTer already provides this communication, so just need to add linux app servicing Next commands.
AFAIK RPi is optional feature. It has nothing to do with ZX emulation.

[antonie]

Need to see what communication channel is used for RPi. If it's UART then MiSTer already provides this communication, so just need to add linux app servicing Next commands.
AFAIK RPi is optional feature. It has nothing to do with ZX emulation.

Yup, agreed. It is only available on the "accelerated" version of the SpecNext. Just curious to see how far the port would go.

[benitoss]

Need to see what communication channel is used for RPi. If it's UART then MiSTer already provides this communication, so just need to add linux app servicing Next commands.
AFAIK RPi is optional feature. It has nothing to do with ZX emulation.

The communication channel used between the FPGA and Pi is serial (UART), but the Pi transmit the audio back to the FPGA through a I2S cahnnel.
This is the basic communication to playing TZX with the Pi or for playing audio and mod files with the PI
Regards

[benitoss]

if some app/game will change layer 2 position very fast, then you won't have time to re-load layer2 into BRAM.
256x192 is standard Spectrum dot clock 7MHz. SDRAM is 16bit, so every word will be fetched at 3.5MHz. If you will use 2-word burst then fetch will be every 1.75MHz. This is pretty much comfortable access time for SDRAM working at around 112MHz. So you don't need to use VRAM. You can fetch layer2 directly from SDRAM.

there is another strategy for MiSTer: use DDR3 for layer2. DDR3 should be write only from CPU. Write access to DDR3 is usually immediate as you don't have to wait for data. The video system will fetch the video data sequentially, so you can add burst mode to fetch for example a whole line to BRAM buffer and while it renders the line from BRAM to screen, you can prefetch another line from DDR3 to second BRAM buffer.

So, there are several ways to handle the video buffer.

Thanks for the answer. I appreciate it
Could you give me a core example of your first strategy ?

Regards

[benitoss]

Here You have the two screens of configuration

photo_2020-06-10_22-54-09.jpg (177.29 KiB) Viewed 15853 times

photo_2020-06-10_22-54-19.jpg (162.37 KiB) Viewed 15853 times

Everything is working now ( VGA (15 Khz and 31 Khz), HDMI, Keyboard, joysticks, sound , and the second SD or VHD file) unless the 2 MB of memory in SDRAM.
All tests done in BRAM (maximum 400 Kb available) are good but the system has not enough memory to start the menu system.
If I solve the SDRAM memory issue the core is gonna work perfectly.

Later I can add the RTC, the UART WIFI and simulate the PI system with a UART and I2S connection (very similar that the emulation of the Munt is doing in the ao486 core, in fact we can use similar program that the Pi uses)

Regards

[Chris23235]

Will it only work with a second SD card in the I/O board, or will it also work with an USB HDD or a card that is connected via a USB hub?

[antonie]

Here You have the two screens of configuration

photo_2020-06-10_22-54-09.jpg

photo_2020-06-10_22-54-19.jpg

Everything is working now ( VGA (15 Khz and 31 Khz), HDMI, Keyboard, joysticks, sound , and the second SD or VHD file) unless the 2 MB of memory in SDRAM.
All tests done in BRAM (maximum 400 Kb available) are good but the system has not enough memory to start the menu system.
If I solve the SDRAM memory issue the core is gonna work perfectly.

Later I can add the RTC, the UART WIFI and simulate the PI system with a UART and I2S connection (very similar that the emulation of the Munt is doing in the ao486 core, in fact we can use similar program that the Pi uses)

Regards

Really great work @benitoss...can't wait to compare your core to my actual SpecNext.

[benitoss]

To accelerate the implementation of the ZX Next core I have published in my GitHub the actual core.
https://github.com/benitoss/ZXNext_Mister

The core needs to use the second SD or the VHD image that you can get here : https://github.com/benitoss/ZXNext_Mist ... xt_vhd.zip

Actually it only uses 400 Kb of BRAM Memory, we only need implement 2 MB using SDRAM and it will Work

Regards

[ron]

@benitoss, great work mate ! , We just need to know how to correctly instantiate that SDRAM

[jordi]

Would like having it.

[benitoss]

One important thing to point out !!!
The original file zxnext_top_issue2.vhd (similar to our zxnext_Mister.vhd file ), in line 1011, has defined the address as

Code: Select all

sram_addr <= (zxn_ram_a_addr(20) & zxn_ram_a_addr(0) & zxn_ram_a_addr(19 downto 1)) when zxn_ram_b_req = '0' else (zxn_ram_b_addr(20) & zxn_ram_b_addr(0) & zxn_ram_b_addr(19 downto 1));

In my code, I use the address in sequential mode to facilitate to read the data in Burst Mode in the SDRAM

Code: Select all

sram_addr <=  zxn_ram_a_addr(20 downto 0)  when zxn_ram_b_req = '0' else zxn_ram_b_addr(20 downto 0);

Regards

[Sorgelig]

Thanks for the answer. I appreciate it
Could you give me a core example of your first strategy ?

Regards

It's quite generic work. Many cores do this. Minimig, Atari ST, SAM Coupe, Archie, TS Conf.

[akeley]

Little question: is there any way to reset current machine from OSD? In my setup this option is greyed out and only becomes available when I change the ZX model.

[killersquirel]

I think it might be F9 or maybe F10 on the keyboard if my memory serves me correctly as I haven't played the ZX Spectrum core on the MiSTer in a week or so. You can change your disk image while a games is running and then press one of those function keys (it might even be F11) and it will reboot.

[Ip75]

All the special keys are near the bottom of this page: https://github.com/MiSTer-devel/ZX-Spectrum_MISTer

It's Ctrl-F11 for a warm reset, Alt-F11 for a hard reset.