this is my 2nd FPGA core for MISTer - another 8-bit Czechoslovakian computer Ondra SPO 186. It's almost fully implemented - only one missing thing is modern HW called Ondra SD for loading SW from SD cards.
Core as it is now is able to load SW from ADC line in and via serial port (user port) with appropriate 3.3V UART converted. If you use higher voltage you fry your mister!
Motivation for using the serial port was:
- it's exactly as it was used on real HW
- Ondra SD is not implemented yet
- I've ported this core to ZX Uno too and therefore I was unable to use all MISTer features like loading files with Linux core
- I was keen to try communication with other world from MISTer
Ondra doesn't bring any extraordinary graphics or unknown games but is interesting inside. Graphics screen generator is very smart. It's done with two 8253 timer generators. These are responsible for HSync and VSync signal as well as counting video ram addresses! Furthermore you can programmatically change screen resolutions. Smart, isn't it? And cheap - and this was at these days important too.
Here is link to github page with few more words about it https://github.com/MiSTer-devel/OndraSPO186_MiSTer
and here is small video showing Ondra core and PC application when loading games into it
And here is link to ZX Uno github https://github.com/PetrM1/OndraSPO186_ZXUno
Ondra SD implementation for easier SW load is in progress...
Enjoy it
Petr
