SparcStation Core
- Alkadian
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Re: SparcStation Core
Also I have just tried Etch, but I get panic error with both L2TBL set to ON and OFF.
I have set IOMMU to 26.
Arghhh!!
EDIT: I have started with a fresh .raw and it has just booted
I have set IOMMU to 26.
Arghhh!!
EDIT: I have started with a fresh .raw and it has just booted
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Re: SparcStation Core
I will try again with NeXTSTEP as it did not look as nice as Etch. When I made my earlier post I said it was not so good and while type went back to look at the post and was surprised it looked so good.
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Re: SparcStation Core
That is the reason I keep a Backup folder on my MISTer, over the years I broke so many disks with this core. Nothing wrong with the core, just OP error.
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- Alkadian
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Re: SparcStation Core
I really do not know what is happening.
I told you that I would post a screenshot of NeXTSTEP to compare with yours. My screen does not look better that yours. I made the screenshot full-screen to also be able to compare it with the one for Linux. I took it with Win + Prt Screen, had a look on my PC with Gimp and guess what? It looks as good as the Linux one. To be sure I changed the view to 100% and it is perfect, text from the image looks as good as the text I am typing right now, it is even better as the image text is a little bold. How is it possible? I will have to revisit Linux which seemed to be a little better than NeXTSTEP.
In a previous post I said this about the Linux screenshot "I just had a look back and for this OS it is very good."
When I wrote that I was impressed by the quality of the text and I said to myself: "It looks better than I remember", now I know why.
I don't really know the reason but when looking at MISTer screenshots on the forum one has to ask himself if what he sees is really what is seen on the MISTer screen.
I know there are 2 ways to take screenshot, one involving the scaler and the other not or something like that.
Experiment coming some time later today.
I told you that I would post a screenshot of NeXTSTEP to compare with yours. My screen does not look better that yours. I made the screenshot full-screen to also be able to compare it with the one for Linux. I took it with Win + Prt Screen, had a look on my PC with Gimp and guess what? It looks as good as the Linux one. To be sure I changed the view to 100% and it is perfect, text from the image looks as good as the text I am typing right now, it is even better as the image text is a little bold. How is it possible? I will have to revisit Linux which seemed to be a little better than NeXTSTEP.
In a previous post I said this about the Linux screenshot "I just had a look back and for this OS it is very good."
When I wrote that I was impressed by the quality of the text and I said to myself: "It looks better than I remember", now I know why.
I don't really know the reason but when looking at MISTer screenshots on the forum one has to ask himself if what he sees is really what is seen on the MISTer screen.
I know there are 2 ways to take screenshot, one involving the scaler and the other not or something like that.
Experiment coming some time later today.
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Re: SparcStation Core
It's surprisingly difficult to make meaningful comparisons between different manufacturers' FPGAs (probably deliberately so!) and gates and logic elements aren't the same thing. That Cray project originated in 2011 - so any comments about the largest affordable FPGA don't necessarily hold true a decade later. I'm reasonably sure a core which fits on the Spartan 3E 1600 would fit the MiSTer two or three times over.LamerDeluxe wrote: ↑Sun Apr 03, 2022 6:38 pm 110K gates on the Cyclone V versus 1600K on the Spartan, so sadly it seems not at all.
Sad to hear the software wasn't archived. Hopefully enough of it will be recovered.
The Sparcstation core looks *extremely* cool - I definitely want to play with this!
- LamerDeluxe
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Re: SparcStation Core
Ah, thanks for the information, I had no idea. That is good to hear, having a Cray core on MiSTer would be amazing.robinsonb5 wrote: ↑Tue Apr 05, 2022 11:58 amIt's surprisingly difficult to make meaningful comparisons between different manufacturers' FPGAs (probably deliberately so!) and gates and logic elements aren't the same thing. That Cray project originated in 2011 - so any comments about the largest affordable FPGA don't necessarily hold true a decade later. I'm reasonably sure a core which fits on the Spartan 3E 1600 would fit the MiSTer two or three times over.LamerDeluxe wrote: ↑Sun Apr 03, 2022 6:38 pm 110K gates on the Cyclone V versus 1600K on the Spartan, so sadly it seems not at all.
Sad to hear the software wasn't archived. Hopefully enough of it will be recovered.
Re: SparcStation Core
There is some talk on the NetBSD list about needing Sparc V7 hardware (and also SMP v7 hardware) to test on to continue to maintain sun-4 and sun-4c support. Do you think it would be possible to reconfigure the design that way? Theoretically it should just be disabling certain features in temlib I would imagine you may also fit 4x cores with the reduced ALU size also.Grabulosaure wrote: ↑Wed Mar 30, 2022 11:12 pm SS20 seems to work with NetBSD with 3 CPUs. This is quite complex code and difficult to validate. Linux hardy ever supported multicore on these computers. I would like to be able to run multicore Solaris.
IIRC, the debug monitor (/soft/debugarm) is currently needed to properly activate SMP mode.
Basically it would need to be an IPX or SS2 like machine (or 600MP or SS20). SS20 actually can be a v7 SMP machine with late revision v7 sbus CPUs though it wasn't officially supported.
Note they aren't talking about dropping support just yet... just a call out for testers with hardware and it would be easier if we could just send them new compatible hardware.
Re: SparcStation Core
Thanks for this core! I worked on a SparcStation 5 for years.Grabulosaure wrote: ↑Wed Mar 30, 2022 11:12 pm SS5 is compatible with all the OSes which supported actual Sun4m SparcStations : Linux, NetBSD, OpenBSD, SunOS, Solaris, NextSTEP. Some OSes requires a special configuration.
Is there a special configuration required to boot Solaris and SunOS? I think I've tried every combination at this point.
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Re: SparcStation Core
It is amazing!
I immediately went to my parents' house to bring the Solaris 8 installation disc.
By the way, is the "L-1" key mapped somewhere? I think that "L-1 + a" will be used in various situations such as installation.
I immediately went to my parents' house to bring the Solaris 8 installation disc.
By the way, is the "L-1" key mapped somewhere? I think that "L-1 + a" will be used in various situations such as installation.
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Re: SparcStation Core
Doing some testing before I submit a PR. So far every OS boots after the change.
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Re: SparcStation Core
I've updated the SS core, changed SCSI ID, and have briefly tested RedHat, Solaris 7, Solaris 8, SunOS, NextSTEP.
I don't understand why it was necessary to change SCSI.
http://temlib.org/pub/mister/SS/ss5.rbf
http://temlib.org/pub/mister/SS/ss20.rbf
It's better to reboot MiSTer when trying different OSes, probably a few missing register reset.
I've also disabled as default The L2TLB which is a pity as it offers something like a 30% speed boost. I think there is some
way to check which OS could support it, or try to find a bug.
There is also the OpenBIOS sources with the changes for this core (original repo. works with QEMU) : https://github.com/Grabulosaure/ss_openbios
When trying different IOMMU rev options, do a core RESET after applying a new value as this is copied by the BIOS into
a configuration structure.
Type "boot" in OpenBIOS prompt if the OS doesn't start right away. And be patient. Keep a backup copy of the OS images on the SD card.
Besides my own bugs, running all these different OSes is a bit tricky because the actual CPUs on SparcStations,
MicroSparcII on SS5 and SuperSparc on SS20 cannot be efficiently implemented exactly the same in a FPGA, and, more
than that, these microprocessors made by Fujistu and Texas Instruments and designed partly by Sun were full of bugs,
particularly in the MMU and cache, so that the Operating Systems had to detect which CPU was present (hence IOMMU rev parameter)
to enable different cache and MMU management code. Awful.
(Just have to read old Linux kernel source code for Sparc32 support, it's full of profanities)
And NextSTEP has some bugs as well, it does weird things during boot and cannot yet be emulated with QEMU.
I didn't expect all these problems when I started this project, a long, long time ago.
It's probably possible to mimic it well enough for OSes to run. And it was probably one of the few early Sparc with no bug. But it's hard to guarantee enough compatibility to get away from "real" hardware.
MiSTer FPGA may be able to fit a fourth CPU when using a module that allows to share one FPU between two CPUs. It's coded but not much tested.
With more recent FPGAs eval boards costing 200$€ to 500€$ it would be possible to be at least as fast as original hardware (100-200MHz). I'd like to test on a small Xilinx UltraScale+ board.
I don't understand why it was necessary to change SCSI.
http://temlib.org/pub/mister/SS/ss5.rbf
http://temlib.org/pub/mister/SS/ss20.rbf
It's better to reboot MiSTer when trying different OSes, probably a few missing register reset.
I've also disabled as default The L2TLB which is a pity as it offers something like a 30% speed boost. I think there is some
way to check which OS could support it, or try to find a bug.
There is also the OpenBIOS sources with the changes for this core (original repo. works with QEMU) : https://github.com/Grabulosaure/ss_openbios
When trying different IOMMU rev options, do a core RESET after applying a new value as this is copied by the BIOS into
a configuration structure.
Type "boot" in OpenBIOS prompt if the OS doesn't start right away. And be patient. Keep a backup copy of the OS images on the SD card.
Besides my own bugs, running all these different OSes is a bit tricky because the actual CPUs on SparcStations,
MicroSparcII on SS5 and SuperSparc on SS20 cannot be efficiently implemented exactly the same in a FPGA, and, more
than that, these microprocessors made by Fujistu and Texas Instruments and designed partly by Sun were full of bugs,
particularly in the MMU and cache, so that the Operating Systems had to detect which CPU was present (hence IOMMU rev parameter)
to enable different cache and MMU management code. Awful.
(Just have to read old Linux kernel source code for Sparc32 support, it's full of profanities)
And NextSTEP has some bugs as well, it does weird things during boot and cannot yet be emulated with QEMU.
I didn't expect all these problems when I started this project, a long, long time ago.
SparcV7 is for the Cypress 7C601 chipset? I actually have the vintage ROSS book.cb88 wrote: ↑Wed Apr 06, 2022 5:13 pmThere is some talk on the NetBSD list about needing Sparc V7 hardware (and also SMP v7 hardware) to test on to continue to maintain sun-4 and sun-4c support. Do you think it would be possible to reconfigure the design that way? Theoretically it should just be disabling certain features in temlib I would imagine you may also fit 4x cores with the reduced ALU size also.Grabulosaure wrote: ↑Wed Mar 30, 2022 11:12 pm SS20 seems to work with NetBSD with 3 CPUs. This is quite complex code and difficult to validate. Linux hardy ever supported multicore on these computers. I would like to be able to run multicore Solaris.
IIRC, the debug monitor (/soft/debugarm) is currently needed to properly activate SMP mode.
Basically it would need to be an IPX or SS2 like machine (or 600MP or SS20). SS20 actually can be a v7 SMP machine with late revision v7 sbus CPUs though it wasn't officially supported.
Note they aren't talking about dropping support just yet... just a call out for testers with hardware and it would be easier if we could just send them new compatible hardware.
It's probably possible to mimic it well enough for OSes to run. And it was probably one of the few early Sparc with no bug. But it's hard to guarantee enough compatibility to get away from "real" hardware.
MiSTer FPGA may be able to fit a fourth CPU when using a module that allows to share one FPU between two CPUs. It's coded but not much tested.
With more recent FPGAs eval boards costing 200$€ to 500€$ it would be possible to be at least as fast as original hardware (100-200MHz). I'd like to test on a small Xilinx UltraScale+ board.
- Alkadian
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Re: SparcStation Core
@ Grabulosaure,
Thank you so much for this new release. Finally Solaris booted perfectly fine!
When you get a chance, could you please advise if there is anything I can edit/change in order to visualise the characters correctly on the screen? They all appear in a sort of very low quality in my case.
Thanks again!
EDIT: I think I have got it! Applying a sharp interpolation filter did the trick.
Thank you so much for this new release. Finally Solaris booted perfectly fine!
When you get a chance, could you please advise if there is anything I can edit/change in order to visualise the characters correctly on the screen? They all appear in a sort of very low quality in my case.
Thanks again!
EDIT: I think I have got it! Applying a sharp interpolation filter did the trick.
Re: SparcStation Core
Been using a new installation of Solaris 7 trying to setup PPP up for network access.
I can confirm Solaris /dev/cua/a is accessible on the MiSTer side from /dev/ttyS1 by echoing some text in both directions. However, I'm having trouble setting up the built-in aspppd software. I think the issue is on the Dialer setting I'm using. I've tried 'direct', ''uudirect' and 'hayes' but have had no luck getting connected. Also tried this script with no luck: http://www.bolthole.com/solaris/configppp.sh
Solaris 8 is supposedly easier to set up with its new PPP client. Trying that next.
I can confirm Solaris /dev/cua/a is accessible on the MiSTer side from /dev/ttyS1 by echoing some text in both directions. However, I'm having trouble setting up the built-in aspppd software. I think the issue is on the Dialer setting I'm using. I've tried 'direct', ''uudirect' and 'hayes' but have had no luck getting connected. Also tried this script with no luck: http://www.bolthole.com/solaris/configppp.sh
Solaris 8 is supposedly easier to set up with its new PPP client. Trying that next.
Re: SparcStation Core
I was able to get Solaris 8 connected over PPP after modifying the Solaris PPP template files. I can even telnet into it from my LAN. . I have attached the PPP config files for Solaris8.
Also attached is a build of SS5 with the UART menu added to enable PPP on the MiSTer, I have submitted a PR for this change.
Solaris 7/8 have been very stable for me. SimCity works great, SunDoom menu loads but crashes when starting a new game, it does this in Qemu as well.
Also attached is a build of SS5 with the UART menu added to enable PPP on the MiSTer, I have submitted a PR for this change.
Solaris 7/8 have been very stable for me. SimCity works great, SunDoom menu loads but crashes when starting a new game, it does this in Qemu as well.
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- Grabulosaure
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Re: SparcStation Core
Congratulations!kconger wrote: ↑Thu Apr 28, 2022 9:09 pm I was able to get Solaris 8 connected over PPP. After modifying the Solaris PPP template files, I had to use this connect script on the MiSTer side: viewtopic.php?p=15634#p15634 . I think there is a way around this by modifying the chat script on the Solaris side, my PPP knowledge is very rusty.
Here is a build of SS5 with the UART menu added to enable PPP on the MiSTer, I have submitted a PR for this change.
Solaris 7/8 have been very stable for me. SimCity works great, SunDoom menu loads but crashes when starting a new game, it does this in Qemu as well.
I didn't ever try PPP. The serial port is used during boot for OpenBIOS messages. It's also used for the hardware debugger (debug program).
The serial port is currently hard-coded at 115200 bits/seconds (src/board/mister/ss_core.vhd, SERIALRATE parameter), and ignores Solaris settings. /dev/ttyS1 seems to support faster speeds, at least 921600 bits/s.
I've also made an Ethernet MAC compatible with RMII PHYs (such as WaveShare LAN8720 module). If anyone is interested I could try to revive that code. It needs 7 signals + GND + 3V3. Maybe possible to reduce to 6 signals and use the "USB" IO port connector.
Re: SparcStation Core
Thanks for developing this core! I used these machines heavily in College and in my first job.Grabulosaure wrote: ↑Thu Apr 28, 2022 11:41 pm Congratulations!
I didn't ever try PPP. The serial port is used during boot for OpenBIOS messages. It's also used for the hardware debugger (debug program).
The serial port is currently hard-coded at 115200 bits/seconds (src/board/mister/ss_core.vhd, SERIALRATE parameter), and ignores Solaris settings. /dev/ttyS1 seems to support faster speeds, at least 921600 bits/s.
I've also made an Ethernet MAC compatible with RMII PHYs (such as WaveShare LAN8720 module). If anyone is interested I could try to revive that code. It needs 7 signals + GND + 3V3. Maybe possible to reduce to 6 signals and use the "USB" IO port connector.
Does the CDROM work at any level? I tried both 512 & 2048 and haven't had any luck.
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Re: SparcStation Core
I updated my PR to limit the speed setting to 115200.Grabulosaure wrote: ↑Thu Apr 28, 2022 11:41 pm The serial port is currently hard-coded at 115200 bits/seconds (src/board/mister/ss_core.vhd, SERIALRATE parameter), and ignores Solaris settings. /dev/ttyS1 seems to support faster speeds, at least 921600 bits/s.
Re: SparcStation Core
SunDoom 1.8 does run! The release notes actually mention the crash as a known issue for this version.
http://web.mit.edu/games/doc/doom/README.sun
AGA frame buffer version does not run. However, the X version does.
To start it up you can do something like this:
Unfortunately, all keys seem to work but the fire key. The notes mention Ctrl, Alt, Meta<>, or Compose. Ctrl closes/crashes? the game. The other keys don't seem to do anything. Maybe they are not mapped in the core yet? I also have the same behavior when I test in QEMU.
http://web.mit.edu/games/doc/doom/README.sun
AGA frame buffer version does not run. However, the X version does.
To start it up you can do something like this:
Code: Select all
sunxdoom -nosound -warp 1
- Newsdee
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Re: SparcStation Core
I haven't been able to find a Sparc binary of it If you happen to find one let me know and I can test.
Tested a few other games. Wolf3D and SOD are both slow and crash. LAND works well. Found a note on how to fix Sundoom crashing and fire key. It plays really well.
@Grabulosaure are there plans to implement audio?
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Re: SparcStation Core
Are you able to build it from source? I've found this:
https://sourceforge.net/projects/xpilot ... lot-4.5.5/
Re: SparcStation Core
I was able to compile it. I don't think there are servers to connect to? The built-in server hostname it fails to connect to.Newsdee wrote: ↑Mon May 02, 2022 2:55 amAre you able to build it from source? I've found this:
https://sourceforge.net/projects/xpilot ... lot-4.5.5/
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Re: SparcStation Core
Does it work with a local server at least? From the INSTALL.TXT file:
Code: Select all
Start a server first:
xpilots -map globe.map
Then start a client in another window:
xpilot
http://www.j-a-r-n-o.nl/xpilotwarning.html
But I found page that lists several servers that are seemingly up!
http://xpilot.netarbeiter.com/
If that fails, this page has a few maps (maps are just the image) that could be run locally:
http://budwin.net/insectoid/xpilot/xpcmaps.html
Even if it is only to run it as a LAN game, it would be neat to resurrect XPilot for MiSTer