MiSTer Core Dev Episode 12: Display + CPU

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nico24
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MiSTer Core Dev Episode 12: Display + CPU

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Looking at how contested VRAM access is handled between display and CPU circuitry in hardware and then in Verilog for the MiSTer. I put the logic analyzer on the circuit to see what's going on.

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Alkadian
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Re: MiSTer Core Dev Episode 12: Display + CPU

Unread post by Alkadian »

Awesome, thanks for this new episode!
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