Looking at how RAM, ROM and peripherals are addressed by the 6502 in our core and then review of the Verilog for the MiSTer. Finally we launch the actual core for the first time.
MiSTer Core Dev Episode 13: Addressing
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MISTerMark
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nico24
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Re: MiSTer Core Dev Episode 13: Addressing
@Alkadian,
Thanks!! At the beginning of the week I was getting way more subscribers than typical, so I thought something was up. I did a search and found that Hackaday article. Great to have the coverage! We're close to getting a working core, just minus the sound for now. So that's going to be fun trying to implement that.
Thanks!! At the beginning of the week I was getting way more subscribers than typical, so I thought something was up. I did a search and found that Hackaday article. Great to have the coverage! We're close to getting a working core, just minus the sound for now. So that's going to be fun trying to implement that.
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Alkadian
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Re: MiSTer Core Dev Episode 13: Addressing
Cool! Looking forward to the next episodes and keep up the great job!nico24 wrote: ↑Sat May 14, 2022 2:19 pm @Alkadian,
Thanks!! At the beginning of the week I was getting way more subscribers than typical, so I thought something was up. I did a search and found that Hackaday article. Great to have the coverage! We're close to getting a working core, just minus the sound for now. So that's going to be fun trying to implement that.