MiSTer PCXT

[kitune-san]

Because they originally carry the 'n', I understand that they work in reverse, 1 = disabled and 0 = enabled. Since the KFPC-XT signals do not, I assumed that they had to be negated.

Sorry. I should have added _n.
signal inversion is not required.

[spark2k06]

A bug was found in RAM.sv of KFPC-XT.
The RAM access range was 00000h-9FFFFFh, but it was 00000h-7FFFFFh.
An error may have occurred when accessing 80000h-9FFFFFh.

https://github.com/kitune-san/KFPC-XT/c ... 4cfde55893

Good point, but in this case it is not the problem. Before using SDRAM I was using 256KB of BRAM, and the BIOS detects and reports the amount of memory available, even with that bug, it should identify and be able to use 512KB without any problem.

[pgimeno]

Thank you both, I will take your advice into account. On another note, I have tried to add the SDRAM signals to have 640KB + HMA available initially:

HMA?

That's an AT thing, not an XT thing.

[spark2k06]

Thank you both, I will take your advice into account. On another note, I have tried to add the SDRAM signals to have 640KB + HMA available initially:

HMA?

That's an AT thing, not an XT thing.

Sorry, UMA

https://en.m.wikipedia.org/wiki/Upper_memory_area

[kitune-san]

Perhaps writing to the SDRAM may have started before the CPU data bus changes.

[kitune-san]

The following changes are being considered.
https://github.com/kitune-san/KFPC-XT/c ... 17e7ffd6c7

RAM.sv and KFSDRAM.sv works in my DE0-CV.

[spark2k06]

The following changes are being considered.
https://github.com/kitune-san/KFPC-XT/c ... 17e7ffd6c7

RAM.sv and KFSDRAM.sv works in my DE0-CV.

It still doesn't work, I update your changes in the specific branch to address this issue:

https://github.com/spark2k06/PCXT_MiSTe ... sdram-test

Don't worry, you've already done enough in this regard, we'll find the cause at some point

It must be something specific to the signal configuration of the MiSTer.

[spark2k06]

beta 0.4

* Added Adlib FM (JTOPL2)
* Added SN76489AN (PCjr Sound)
* Change to alternative BIOS from PCXT version 0.9.8 developed by Sergey Kiselev, with OPL FM sound card detector

https://github.com/spark2k06/PCXT_MiSTer

[kitune-san]

The following changes are being considered.
https://github.com/kitune-san/KFPC-XT/c ... 17e7ffd6c7

RAM.sv and KFSDRAM.sv works in my DE0-CV.

It still doesn't work, I update your changes in the specific branch to address this issue:

https://github.com/spark2k06/PCXT_MiSTe ... sdram-test

Don't worry, you've already done enough in this regard, we'll find the cause at some point

It must be something specific to the signal configuration of the MiSTer.

Oh...
Can the SDRAM I/O Standard be changed to 3.3V LVTTL?
That's all I can come up with now.

[spark2k06]

Oh...
Can the SDRAM I/O Standard be changed to 3.3V LVTTL?
That's all I can come up with now.

This is how it was already configured:

SDRAM_IO_STANDAR.png (9.59 KiB) Viewed 26167 times

This is the section of BIOS code that does a memory check on the first 32Kb. As you can see, it is by writing and checking the 55AAh pattern, and then AA55h... all by rep stosw and lodsw respectively. As soon as I set up the dynamic BIOS loading, I will test more thoroughly and take advantage of the POST I/O port 80h for debugging. I will intercept it from the core and use the 8 MiSTer LEDs for display... another possibility would be to use the DEBUG serial port to output the codes:

Code: Select all

;-------------------------------------------------------------------------
; Test first 32 KiB (MIN_RAM_SIZE) of RAM

	mov	al,e_low_ram_test
	out	post_reg,al
	xor	si,si
	xor	di,di
	mov	ds,di
	mov	es,di
	mov	dx,word [warm_boot+biosdseg*16] ; save soft reset flag to DX
	mov	ax,55AAh		; first test pattern
	mov	cx,MIN_RAM_SIZE*512	; RAM size to test in words
    rep	stosw				; store test pattern
	mov	cx,MIN_RAM_SIZE*512	; RAM size to test in words
.1:
	lodsw
	cmp	ax,55AAh		; compare to the test pattern
	jne	low_ram_fail
	loop	.1
	xor	si,si
	xor	di,di
	mov	ax,0AA55h		; second test pattern
	mov	cx,MIN_RAM_SIZE*512	; RAM size to test in words
    rep stosw				; store test pattern
	mov	cx,MIN_RAM_SIZE*512	; RAM size to test in words
.2:
	lodsw
	cmp	ax,0AA55h		; compare to the test pattern
	jne	low_ram_fail
	loop	.2
	xor	di,di
	xor	ax,ax			; zero
	mov	cx,MIN_RAM_SIZE*512	; RAM size to test in words
    rep stosw				; zero the memory
	jmp	low_ram_ok		; test passed

low_ram_fail:
	mov	al,e_low_ram_fail	; test failed
	out	post_reg,al

;-------------------------------------------------------------------------
;  Low memory error: beep - pause - beep - pause ... - 400 Hz

	mov	al,0B6h
	out	pit_ctl_reg,al		; PIT - channel 2 mode 3
	mov	ax,pic_freq/400		; 400 Hz signal
	out	pit_ch2_reg,al
	mov	al,ah
	out	pit_ch2_reg,al
	in	al,ppi_pb_reg
.1:
	or	al,3			; turn speaker on and enable
	out	ppi_pb_reg,al		; PIT channel 2 to speaker
	mov	cx,0
.2:
	nop
	loop	.2
	and	al,0FCh			; turn of speaker
	out	ppi_pb_reg,al
	mov	cx,0
.3:
	nop
	loop	.3
	jmp	.1

[kitune-san]

It still doesn't work, I update your changes in the specific branch to address this issue:

https://github.com/spark2k06/PCXT_MiSTe ... sdram-test

Don't worry, you've already done enough in this regard, we'll find the cause at some point

It must be something specific to the signal configuration of the MiSTer.

Have you changed any of the following？

Code: Select all

	assign SDRAM_nCS = ~SDRAM_CS;
	assign SDRAM_nCAS = ~SDRAM_CAS;
	assign SDRAM_nRAS = ~SDRAM_RAS;
	assign SDRAM_nWE = ~SDRAM_WE;

Inversion is not necessary.

Code: Select all

	assign SDRAM_nCS = SDRAM_CS;
	assign SDRAM_nCAS = SDRAM_CAS;
	assign SDRAM_nRAS = SDRAM_RAS;
	assign SDRAM_nWE = SDRAM_WE;

[spark2k06]

I did, yes, but the result is the same, it does not pass the initial 32Kb memory test.

Have you changed any of the following？

Code: Select all

	assign SDRAM_nCS = ~SDRAM_CS;
	assign SDRAM_nCAS = ~SDRAM_CAS;
	assign SDRAM_nRAS = ~SDRAM_RAS;
	assign SDRAM_nWE = ~SDRAM_WE;

Inversion is not necessary.

Code: Select all

	assign SDRAM_nCS = SDRAM_CS;
	assign SDRAM_nCAS = SDRAM_CAS;
	assign SDRAM_nRAS = SDRAM_RAS;
	assign SDRAM_nWE = SDRAM_WE;

[spark2k06]

What I am not so sure about is this:

Code: Select all

assign SDRAM_DQ_IN = SDRAM_DQ;
assign SDRAM_DQ = ~SDRAM_DQ_IO ? SDRAM_DQ_OUT : 16'hZZ;

[spark2k06]

I've managed to get the rom loading via ioctl working, now it will be easier to debug

https://github.com/spark2k06/PCXT_MiSTe ... ioctl-test

@pgimeno, do you know any debugger that doesn't require DOS functions? That works without any problem only with the BIOS functions? One that can load in memory without problems.

[pgimeno]

@pgimeno, do you know any debugger that doesn't require DOS functions? That works without any problem only with the BIOS functions? One that can load in memory without problems.

I don't know any, I've always used debuggers from DOS.

QA (Quaid Analyzer) is quite close; it only seems to make a single DOS call when running (if you don't use the functions to dump memory to file), but it also uses DOS to terminate and stay resident. So one strategy could be to add an INT 21h interrupt handler that emulates DOS functions 34h and 31h.

Problem is, it's an .exe file and you have to load it. According to the exe header it has no relocations, but it has a different SS:SP on load. The initial CS:IP is the same as in a .com file.

So, I could prepare an in-memory image of QA with a fake PSP that passes the parameter 5 to it (executing "qa 5" from the DOS command line makes it trap interrupt 5 as a trigger, to start debugging with PrtSc), and also a fake INT 21h handler; if you're able to load that image to memory, here are the steps that would be necessary in order to run it:

- It will be loaded in a fixed segment at offset 0.
- You need to set up SS=that segment + 1375h, SP=100h, and jump to that segment at address 100h. So, if the segment is, say, 1000h, you would set up SS=2375h, SP=100h and jump to 1000h:0100h. Just let me know what segment. Take into account that once resident, QA uses about 107 KB of RAM. Of course, since it uses RAM, it needs a working RAM.
- The INT 21h function 31h fake handler will return to the BIOS; you need to tell me how to find the address where it needs to jump. It can be a pointer that you store in ROM at a certain fixed address. EDIT: If you want it to debug the reset sequence, it can jump to FFFF:0000.
- At that address you will place an INT 05h. That will trigger QA and allow you to single-step from there. EDIT: I'm thinking that the INT 21h handler could itself call INT 05h then jump to the BIOS, so that the BIOS doesn't need to be changed.

[spark2k06]

Thanks.

I could reserve 32Kb of BRAM in segment 0, the minimum needed to pass the BIOS RAM test, and also 128Kb, with segment D000 and E000 full.

If you prepare that image for me, then from the BIOS I can prepare the stack and jump to the necessary point.

[pgimeno]

I've sent you a PM.

[kitune-san]

What I am not so sure about is this:

Code: Select all

assign SDRAM_DQ_IN = SDRAM_DQ;
assign SDRAM_DQ = ~SDRAM_DQ_IO ? SDRAM_DQ_OUT : 16'hZZ;

It is necessary to ensure that the two outputs do not collide.

16'hzzzz" is more accurate than "16'hzz".

[kitune-san]

Could you please show me your latest SDC file?

[spark2k06]

I have tried it and the same result, RAM failure.

It is necessary to ensure that the two outputs do not collide.

16'hzzzz" is more accurate than "16'hzz".

How do I regenerate those files from Quartus, because starting from a new compilation, they are not updated...

Could you please show me your latest SDC file?

[spark2k06]

There are many MiSTer cores that make use of SDRAM, maybe if you check some of them, like this SNES one you can see something I don't see, comparing both projects:

https://github.com/MiSTer-devel/SNES_MiSTer

[kitune-san]

How do I regenerate those files from Quartus, because starting from a new compilation, they are not updated...

Could you please show me your latest SDC file?

Synopsys Design Constraints (.sdc) files are created by the designer. It is not generated.
Even if SDC was not the cause of this problem, this file should be created.
Also needed for timing analysis.

[kitune-san]

By the way, is the CPU clock at the time of RAM check 4.77MHz?

[spark2k06]

Synopsys Design Constraints (.sdc) files are created by the designer. It is not generated.
Even if SDC was not the cause of this problem, this file should be created.
Also needed for timing analysis.

SDC Files.png (10.84 KiB) Viewed 25685 times

If they are not generated, then all of them are available in the repository:

https://github.com/spark2k06/PCXT_MiSTe ... sdram-test

The largest file, 3Kb is sys_top.sdc

By the way, is the CPU clock at the time of RAM check 4.77MHz?

I have tried both 4.77Mhz and 7.16Mhz... in neither case has it passed the test.

[spark2k06]

Eureka!

The memory test has been passed. The SDRAM_CLK signal was not connected!!!, moreover, indeed @kitune-san, the SDRAM_n* signals must be passed to the RAM module without negating, you were right:

https://github.com/spark2k06/PCXT_MiSTe ... sdram-test

Although it passes the test, because the Intel inside bong sounds, then the BIOS screen does not appear, possibly due to the address assignment, I'll check it.

[kitune-san]

I will fix the SDRAM.sv because the self refresh operation is not working.
CKE is not LOW during the refresh command.

[spark2k06]

I will fix the SDRAM.sv because the self refresh operation is not working.
CKE is not LOW during the refresh command.

Great. Yes, because although it passes the test, it doesn't seem to work very well, I haven't managed to get the initial BIOS screen to come up.

[kitune-san]

Sorry. I Mistake.
KFSDRAM.sv uses auto-refresh, not self-refresh.
No modifications.

However, I will look into it some more.

[kitune-san]

Could you tell me what SDRAM chip you are using?

[kitune-san]

Could you tell me what SDRAM chip you are using?

I will not modify the refresh, but increasing the parameter time may stabilize the operation.