MicroCoreLabs wrote: ↑Sat Jun 11, 2022 6:26 am
I suggest looking at the SuperSoft manual for their explanation why Interrupt Level 0 fails. This test appears to cover the 8253, 8259, and the 8288.
MiSTer PCXT
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Re: MiSTer PCXT
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Re: MiSTer PCXT
And this would be the SuperSoft code that fails the test:
It seems to be a timing issue.
It seems to be a timing issue.
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Re: MiSTer PCXT
In mode 0, if the count register is rewritten during counting, it stops.
Then, a second rewrite starts the count.
Apparently I have not incorporated this specification....
However, I do not know if this is the cause of this issue.
Then, a second rewrite starts the count.
Apparently I have not incorporated this specification....
However, I do not know if this is the cause of this issue.
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Re: MiSTer PCXT
That could explain why before the timer fix, this test worked? This is why I am leaning towards something to do with the timing.kitune-san wrote: ↑Sat Jun 11, 2022 9:29 am In mode 0, if the count register is rewritten during counting, it stops.
Then, a second rewrite starts the count.
Apparently I have not incorporated this specification....
However, I do not know if this is the cause of this issue.
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Re: MiSTer PCXT
I think there is no change in the start/stop timing of the counter before and after the timer fix.
It is a wonder that the timer passed before the modification.
It is a wonder that the timer passed before the modification.
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Re: MiSTer PCXT
It is unlikely, but would you like to try timing constraints?
The clocks clk_14_318, clk_4_77, and peripheral_clock are not output from the PLL, so create_generated_clock is required.
For example: (As a reminder, this is not perfect.)
https://github.com/kitune-san/PCXT_MiST ... 2402da06ef
Note that the processing time of Fitter is very long.
The clocks clk_14_318, clk_4_77, and peripheral_clock are not output from the PLL, so create_generated_clock is required.
For example: (As a reminder, this is not perfect.)
https://github.com/kitune-san/PCXT_MiST ... 2402da06ef
Note that the processing time of Fitter is very long.
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Re: MiSTer PCXT
I have generated the clk_cpu and peripheral_clock using PLLs with the wizard, finally I dispense with the 14_318 and 7_16 signals because I don't really need them, the 14_318 one was only used for the splash screen, and I can use the clk_cpu one for it without any problem:kitune-san wrote: ↑Sat Jun 11, 2022 11:47 am It is unlikely, but would you like to try timing constraints?
The clocks clk_14_318, clk_4_77, and peripheral_clock are not output from the PLL, so create_generated_clock is required.
For example: (As a reminder, this is not perfect.)
https://github.com/kitune-san/PCXT_MiST ... 2402da06ef
Note that the processing time of Fitter is very long.
Indeed, the fitter time has increased from 8 minutes to 20 minutes, but the test failure still occurs.
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Re: MiSTer PCXT
Thank you for trying it. hmm...
I remembered that the output of timer 1 is not connected to the input of the DMA request because I didn't think old DRAM was necessary.
in Chipset.sv
This wiring is expected to slightly increase processing time.
I remembered that the output of timer 1 is not connected to the input of the DMA request because I didn't think old DRAM was necessary.
in Chipset.sv
Code: Select all
BUS_ARBITER u_BUS_ARBITER (
....
.dma_request ({dma_request[2:0]}, timer_counter_out[1]},
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Re: MiSTer PCXT
in Chipset.svkitune-san wrote: ↑Sat Jun 11, 2022 3:55 pm Sorry, DMA needed FF between timer output and DRQ.
Please wait a moment.
Code: Select all
always_ff @(negedge clock) begin
prev_timer_count_1 <= timer_counter_out[1];
end
always_ff @(negedge clock, posedge reset) begin
if (reset)
DRQ0 <= 1'b0;
else if (~dma_acknowledge_n[0])
DRQ0 <= 1'b0;
else if (~prev_timer_count_1 & timer_counter_out[1])
DRQ0 <= 1'b1;
else
DRQ0 <= DRQ0;
end
BUS_ARBITER u_BUS_ARBITER (
....
.dma_request ({dma_request[3:1]}, DRQ0},
....
);
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Re: MiSTer PCXT
Tested... nothing, the test failure still occurs. Don't worry about it, we are waiting for you to get the MiSTerkitune-san wrote: ↑Sat Jun 11, 2022 4:11 pmin Chipset.svkitune-san wrote: ↑Sat Jun 11, 2022 3:55 pm Sorry, DMA needed FF between timer output and DRQ.
Please wait a moment.Code: Select all
always_ff @(negedge clock) begin prev_timer_count_1 <= timer_counter_out[1]; end always_ff @(negedge clock, posedge reset) begin if (reset) DRQ0 <= 1'b0; else if (~dma_acknowledge_n[0]) DRQ0 <= 1'b0; else if (~prev_timer_count_1 & timer_counter_out[1]) DRQ0 <= 1'b1; else DRQ0 <= DRQ0; end BUS_ARBITER u_BUS_ARBITER ( .... .dma_request ({dma_request[3:1]}, DRQ0}, .... );
Thank you!
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Re: MiSTer PCXT
MiSTer has been delivered to me.
At first, SuperSoftROM was booted and I was connected to the Signal Tap.
I will report back if I find out anything.
At first, SuperSoftROM was booted and I was connected to the Signal Tap.
I will report back if I find out anything.
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Re: MiSTer PCXT
Good news! You'll let us know . Please do not hesitate to send me a pull request for any further developments.kitune-san wrote: ↑Sun Jun 12, 2022 3:47 am MiSTer has been delivered to me.
At first, SuperSoftROM was booted and I was connected to the Signal Tap.
I will report back if I find out anything.
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Re: MiSTer PCXT
Apparently, an interrupt request is received before int0 starts counting...
Start investigating 8259.
Start investigating 8259.
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Re: MiSTer PCXT
CGA and MDA at the same time for the MiSTer PCXT core. Thanks to Graphics Gremlin from TubeTimeUS... I still need to investigate how to display it in HDMI and VGA at the same time, as an additional option:
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Re: MiSTer PCXT
That would be fine but from EGA onwards it gets quite complicated, in addition to the FPGA implementation you have to add a BIOS that adds the corresponding functions. I hope that once we have an advanced version of a PCXT, this can be part of the official repository of MiSTer and from then on other developers will be encouraged to add functions, precisely because of space there won't be any problem.
However, as far as the graphics features are concerned, I still want to squeeze more out of the current Graphics Gremlin development, i.e. composite video output and colour burst, and improve the Tandy features, which was only halfway there.
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Re: MiSTer PCXT
Floppy is perhaps more simple to implement
There is a lot of booter floppy disk to try
There is a lot of booter floppy disk to try
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Re: MiSTer PCXT
Love to see this thing grow as openly as you are building it. Absolutely +1 on the Tandy. For nostalgia I'd drool over a working Hercules output as well but you do what you deem best. Thank you for the massive effort!
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Re: MiSTer PCXT
Beta 0.8
https://github.com/spark2k06/PCXT_MiSTe ... d211158808
https://github.com/spark2k06/PCXT_MiSTer/tree/fdd-test
https://github.com/spark2k06/PCXT_MiSTe ... d211158808
- MDA and CGA/Tandy now work at the same time. It is possible to switch from one to the other from the OSD menu, as well as their monochrome simulation independently.
- Fixed problem with INT0 test failing
- Fixed a bug that caused the timer counter to be cleared on latch.
- PCXT DIP switches and access to MDA memory
- Add port_b[6] to lock PS/2 CLK.
- PS/2 CLK to drop LOW after receiving the key code.
I would like to, but it is not an easy task, and at the moment it is out of my reach. I've mentioned it to @JasonA to see if he can take a look at it, it would certainly make the core more usable for all users.
It is simpler in principle than IDE, and I actually made a first attempt, but I got stuck with the 16-bit handling in the HPS part of MiSTer:breiztiger wrote: ↑Sun Jun 12, 2022 8:09 pm Floppy is perhaps more simple to implement
There is a lot of booter floppy disk to try
https://github.com/spark2k06/PCXT_MiSTer/tree/fdd-test
Yes, Hercules is another interesting option to evaluate in the future
Re: MiSTer PCXT
I'm not sure if @sorgelic could take a look on this floppy integration. I guess it would be simple for the authorspark2k06 wrote: ↑Mon Jun 13, 2022 4:57 am Beta 0.8
https://github.com/spark2k06/PCXT_MiSTe ... d211158808
- MDA and CGA/Tandy now work at the same time. It is possible to switch from one to the other from the OSD menu, as well as their monochrome simulation independently.
- Fixed problem with INT0 test failing
- Fixed a bug that caused the timer counter to be cleared on latch.
- PCXT DIP switches and access to MDA memory
- Add port_b[6] to lock PS/2 CLK.
- PS/2 CLK to drop LOW after receiving the key code.
I would like to, but it is not an easy task, and at the moment it is out of my reach. I've mentioned it to @JasonA to see if he can take a look at it, it would certainly make the core more usable for all users.
It is simpler in principle than IDE, and I actually made a first attempt, but I got stuck with the 16-bit handling in the HPS part of MiSTer:breiztiger wrote: ↑Sun Jun 12, 2022 8:09 pm Floppy is perhaps more simple to implement
There is a lot of booter floppy disk to try
https://github.com/spark2k06/PCXT_MiSTer/tree/fdd-test
Yes, Hercules is another interesting option to evaluate in the future
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Re: MiSTer PCXT
I added keybord reset logic.
With this change, the keyboard controller test would pass.
I have sent you a pull request.
Please try it.