I have forked my own fork of the C128 core, so that I will be working on 2 similar cores.
C128 core will have only stuff on it that would be available on or to a C128. This is where I am currently working on 1571 support and hooking up the fast serial lines. It will also be easier for me to sync up with the main C128 core by keeping this one core "pure".
I will also be working on a core called C128DX. This core is going to deviate alot from the C128 and will probably end up more like the C64DX/C65, though in many ways may end up being better. It will not be compatible with the C65 however, since the C65 is still inherently 8 bit and I am increasingly interested in using the WDC 65832 in C128DX.
This is where I will develop the C128 that Commodore should have given us.
I will be backporting anything directly C128 related back to the C128 pure core, such as the 1571, burst moce, etc.
Now I have a roadmap for the C128DX core, and things that it will have and not have in it.
- The C128DX will drop support for the Z80 and CP/M. This is to save LEs for the 85832 and other enhancements.
- The Sound Expander and Digimax support will be being dropped in favor of my own hardware, the 16581 SID Extreme
[**]https://public.kitsunet.net/832/16581.txt - The CPU will be transitioned to the 65832, a 32 bit version of the 65816 that was developed by WDC but never released. In 8 bit mode, it will be compatible with the 6510/8502, including timing, but NOT with the illegal instructions.
- The C128DX core will be entirely compatible with the SuperCPU 128 ad SuperCPU 64 (in C64 mode) version 2. I do not expect the current C64/128 cores to adopt the SuperCPU, but there is no small amount of demand for it, and since I an *very* familiar with the 65816, I should be able to produce a core that meets that demand.
- The CPU will have an MMU compatible with the C128, but also extended. That work is obviously already done and working, but I will be expanding it further to be a 32 bit MMU.
- The VIC-II will not be touched to maximize compatibility.
- The VDC on the other hand, WILL be touched.
[**] An enhanced VDC with CPU mapped registers and RAM, as well as the compatible $D600/$D601 interface, will be developed.
[**] It will support 320/640/960/1280 * 200/400/600/800 display modes.
[**] It will support Mono, 16 color, 256 color CLUT with transparent color, and 64k RGB565 and 32k RGBA 5551 color modes.
[**] It will not support interlaced modes. Modes that were interlaced will now be 25 or 30hz progressive modes. Interlace is the devil.
Thanks for your patience.