Amiga RTG support (Update: Released!)

[chaos]

hi @chaos , just to ask because the nick is familiar, are you one of the guys that basically created minimig ?

No, I didn't create minimig I did add the AGA support though.

[chaos]

I'd like to help with any of the menial tasks for any of these things.

Perhaps this could be useful to chaos https://github.com/michalsc/Emu68

Great, any support with testing would be appreciated.

[petarku]

hi @chaos , just to ask because the nick is familiar, are you one of the guys that basically created minimig ?

No, I didn't create minimig I did add the AGA support though.

i could connect your name with minimig , so it was AGA i stand corrected. Anyway it is great to have you onboard.

[xolod79]

I'd like to help with any of the menial tasks for any of these things.

Perhaps this could be useful to chaos https://github.com/michalsc/Emu68

Great, any support with testing would be appreciated.

In quality 68040 on the side of ARM it is possible to use implementation from https://github.com/aranym/aranym
It is also used in https://github.com/PandTomB/uae4arm
And
https://github.com/midwan/amiberry

[uigiflip]

@robinsonb5 have emailed you. Let me know what you need and I may come up with something.

[uigiflip]

https://github.com/robinsonb5/MinimigAGA_TC64

robinsonb5 seems to have cracked rtg and akiko

[mbo77]

Interesting, can this work be used to compile a core for MiSTer?

[robinsonb5]

Interesting, can this work be used to compile a core for MiSTer?

At the moment it's just a dumb framebuffer running from the same SDRAM as the Minimig memory (since that's all we have on MiST and TC64) - no blitter or hardware sprite. Max pixel clock of 56.75MHz in 15-bit, and 113.5MHz in 8-bit, but write speed suffers if you max it out.

It shouldn't be difficult to do a direct port - the only complication is that the MiSTer Minimig core currently uses a simplified SDRAM controller which runs at a slower clock rate than the MiST and TC64 ports. To make the RTG mode possible I'm using 8-word bursts and bank interleaving to get as much read bandwidth as possible out of the SDRAM, so for a direct port MiSTer would have to use an equally capable SDRAM controller.
However, if the DDR RAM on the MiSter can be pressed into service, it should be possible to do something significantly better than a direct port.

[mbo77]

As I'm rather new to this whole scene, is there a direct way of running it on the DE10?

[robinsonb5]

As I'm rather new to this whole scene, is there a direct way of running it on the DE10?

Not directly, no - I think it would be as much work to make it run directly as it would be to run within the MiSTer framework - probably more since it assumes the availability of regular rather than DDR SDRAM.

[mbo77]

Forgive my ignorance, but is it functional already somewhere?

[robinsonb5]

Forgive my ignorance, but is it functional already somewhere?

Currently it's only implemented on the Turbo Chameleon 64, which has the same FPGA as the MiST (as opposed to MiSTer) but no supporting host CPU. It shouldn't be too difficult to port to other devices though. (It does also work on the DE10-lite, since I use one of those as a dev platform - but that's a totally different board, not remotely similar to the DE10-nano.)

[kolla]

@robinsonb5
Do you have a MiST yourself to test with?

[robinsonb5]

@robinsonb5
Do you have a MiST yourself to test with?

I do, yes - however I had to make some changes when porting the core to TC64 which broke the MiST build in my repo - I haven't got around to un-breaking it yet!

[limi]

@robinson5 So can we send you a MiSTer to help out?

[robinsonb5]

@robinson5 So can we send you a MiSTer to help out?

Thanks for the offer - it's much appreciated. However, I think wheels are already in motion to bring a MiSTer my way - I'll let you know if for any reason it doesn't happen, if that's OK?

[limi]

Great! Just let us know

[Sorgelig]

Recent MiSTer framework supports framebuffer from DDR3 supplied by core. So the proper way for RTG is to use framebuffer.
Basically it's just another memory region in DDR3 (left some space in DDR3 exactly for RTG). For me, the hardest part is Amiga side, not HDL. Resolution on RTG for MiSTer isn't a problem. Up to 1920x1080 can be easily supported.
Modification is SDRAM is not required. SDRAM is only for Chip RAM.

[uigiflip]

Great! Just let us know

checking if the care package has departed lol

[uigiflip]

Checked will be dispatched next week

[robinsonb5]

For me, the hardest part is Amiga side, not HDL. Resolution on RTG for MiSTer isn't a problem. Up to 1920x1080 can be easily supported.

Well having done it once, the software side's easy for me now.
With the framebuffer approach, does the Amiga still need to set up a CRTC frame with sync/blank counters, or is that all handled host-side with the MiSTer framework?

Modification is SDRAM is not required. SDRAM is only for Chip RAM.

Sure - I did say that would be necessary for a *direct port* of what I already have working - but I realise on the MiSTer there's a better approach.

[Grabulosaure]

@robinsonb5

The idea is to use the scaler to generate the image. You provide image size, colour depth, base address and a switch to activate the thing and it will display your framebuffer instead of the existing MiniMig core output. This is how the framebuffer mode (F9 from menu) works.
(colour depths are 256c indexed, 16bits 565 RGB, 24bits RGB, 32bits RGB_)

Constraint is that line length is rounded to 256 bytes (example 800 pixels, 24bits = 2400 bytes => 2560 bytes per line)

[robinsonb5]

Checked will be dispatched next week

Awesome - many thanks for that.

The idea is to use the scaler to generate the image. You provide image size, colour depth, base address and a switch to activate the thing and it will display your framebuffer instead of the existing MiniMig core output.

OK, so the timings created in Picasso96Mode will be irrelevant - only the dimensions and pixel format will be needed.

Constraint is that line length is rounded to 256 bytes (example 800 pixels, 24bits = 2400 bytes => 2560 bytes per line)

OK, I've just done a quick test and it doesn't look like rounding up the row size will be a problem.

[Sorgelig]

OK, I've just done a quick test and it doesn't look like rounding up the row size will be a problem.

ascal has been changed already current version in template has stride granularity of 16 bytes so it should be not a problem for RTG resolutions.
Soon it will be updated with 1 pixel granularity.
I'm currently working on SVGA in ao486 which is basically similar to RTG on Amiga and uses framebuffer in DDR3.

OK, so the timings created in Picasso96Mode will be irrelevant - only the dimensions and pixel format will be needed.

Yes and no. HSync/Vsync has to be generated anyway from the core as scaler does sync to video. So basically scaler needs to know how fast to draw the video. But anyway it can be simplified as you don't need to generate blanking. Just HSync/Vsync will be enough.

[Grabulosaure]

@robinsonb5
@sorgelig
When using vsync_adjust=2, the scaler (actually a separate block in sys) tries to synchronise input video with scaled output. If the framebuffer mode is used, that same block willl still try to synchronize video, even if the "input video" isn't displayed anymore.
I don't know how RTG boards work, but if some boards used synchro pulses as interrupts, or for double buffering, then the hsync/vsync signals generated by the scaler will be needed as inputs.

[Sorgelig]

@robinsonb5
@sorgelig
When using vsync_adjust=2, the scaler (actually a separate block in sys) tries to synchronise input video with scaled output. If the framebuffer mode is used, that same block willl still try to synchronize video, even if the "input video" isn't displayed anymore.
I don't know how RTG boards work, but if some boards used synchro pulses as interrupts, or for double buffering, then the hsync/vsync signals generated by the scaler will be needed as inputs.

this is why i've wrote above that even in framebuffer mode the core should generate the hsync/vsync.
Getting sync signals from output video back to core is not an universal solution. Some cores may also need hblank/vblank for internal work. Also core may need to generate specific refresh rate instead a standard. So it's better if core will generate hsync/vsync (together with other sync signals if required) and then scaler will sync to it (if asked) as usual.

[Grabulosaure]

@sorgelig @robinsonb5
Besides HSYNC/VSYNC, The DE "Display Enable" is needed for synchronisation (because the scaled image must be aligned with the top or bottom of the input image.

The transparent multi-buffering done by the scaler isn't available in framebuffer mode.
Many options are available, such as ignoring synchronization and allow tearing, or use HDMI sync signals to software in RTG mode, or using that synchro for transparent multi-buffering : This is how works the GBA core in framebuffer mode, using the signal fb_vbl = hdmi_vblk, to synchronize multi-buffer switch with HDMI output : The software always has the original vertical frequency independantly from HDMI video mode, and double-buffering is done by the core instead of the scaler.

[Sorgelig]

Right. This is again toward my original post - core needs to generate its sync signals in framebuffer mode. So it will control multiple buffers itself and scaler will follow the vsync.

[kolla]

Is it at all possible to simultaneously have different outputs on the HDMI and the IO-board analogue port, or are they very much linked together?

[Fularu]

Is it at all possible to simultaneously have different outputs on the HDMI and the IO-board analogue port, or are they very much linked together?

Like RTG via HDMI and 256p via RGB out?