MiSTer PCXT

[dmckean]

Extra horizontal scan resolution doesn't really matter much. 1280 is a multiple of both 320 and 640 and should look fine.

I tested it with a 15khz sony pvm monitor. The top part shakes a lot and breaks. 1280X200 resolution is not normally output on crt monitors or TVs that support 15khz output.

If that's happening there are other problems with the timings. I have a groovemame setup and sometimes we use what's called "super resolutions" which are resolutions like 2560x240 which will work for many, many different arcade games and display perfectly fine on a 15khz monitor.

[suww37]

Extra horizontal scan resolution doesn't really matter much. 1280 is a multiple of both 320 and 640 and should look fine.

I tested it with a 15khz sony pvm monitor. The top part shakes a lot and breaks. 1280X200 resolution is not normally output on crt monitors or TVs that support 15khz output.

If that's happening there are other problems with the timings. I have a groovemame setup and sometimes we use what's called "super resolutions" which are resolutions like 2560x240 which will work for many, many different arcade games and display perfectly fine on a 15khz monitor.

Do you know the proper timing values ​​for PCXT core (1280x200)? I had no problems with the other core 15khz.

[spark2k06]

Of these blocks, what is feasible to move to SDRAM are the 64Kb + 16Kb of BIOS, with a little effort, I think you can use the same RAM controller developed by kitune-san, to preload there the data coming from IOCTL.

A new sdram controller needs to be developed that manages all the callings for RAM, BIOS and VRAM and then accesses R/W the SDRAM

I already saw it, but specifically for the BIOS ROM and XTIDE part, I still think it is possible to use the RAM module already developed by kitune-san, which in turn uses the SDRAM controller also developed by him, for loading from IOCTL at the beginning of the core, when the ioctl_download signal is active... but tests should be carried out to make sure of this.

[spark2k06]

Is it possible to output CGA 15Khz?

The core is outputing 15Khz already but at the wrong resolution. It's related to the issue I talk about in my last post.
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20220719_203613.jpg

I need to double check but I think MDA may be working better. Perhaps the issue is CE_PIXEL=1 is tied to the MDA video frequency. That could be changed (make it tied to CGA), but I do like the ability to use either MDA or CGA. Would be a shame to lose MDA, but maybe just as temporary measure until the video handling can be sorted out properly.

I don't know much about the handling of video in MiSTer, if you make improvements in this regard, a pull request would be welcome

Regarding the CGA resolution, 640x200 should always be used... 320x200 resolutions are actually 640x200 with the pixels doubled.

[spark2k06]

Thank you for testing
I sent a pull request to @spark2k06.

Thank you! Tomorrow I will accept the pull request and leave the two prebeta repositories updated.

Pull request accepted and prebeta-1.5-turbo branch updated with this improvement as well.

[MicroCoreLabs]

I already saw it, but specifically for the BIOS ROM and XTIDE part, I still think it is possible to use the RAM module already developed by kitune-san, which in turn uses the SDRAM controller also developed by him, for loading from IOCTL at the beginning of the core, when the ioctl_download signal is active... but tests should be carried out to make sure of this.

Or maybe:
- locate the 64kb of BIOS ROM range to SDRAM - will be undefined at powerup
- preload the 64KB of CGA and MDA video BRAMs with the BIOS data using the FPGA programming file
- before the 8088 is unreset, copy this data from the video BRAMs to the BIOS address range in SDRAM.

If you plan to support both video controllers using BRAM, then this might be a convenient place to store 64KB of the BIOS data, and then copy it over to SDRAM with a small state machine which runs at powerup.

[spark2k06]

Or maybe:
- locate the 64kb of BIOS ROM range to SDRAM - will be undefined at powerup
- preload the 64KB of CGA and MDA video BRAMs with the BIOS data using the FPGA programming file
- before the 8088 is unreset, copy this data from the video BRAMs to the BIOS address range in SDRAM.

If you plan to support both video controllers using BRAM, then this might be a convenient place to store 64KB of the BIOS data, and then copy it over to SDRAM with a small state machine which runs at powerup.

However, there is a part of this memory that is part of the text mode VRAM, and I use it to display the splash screen.

In any case, these would be solutions aimed at other FPGAs with lower capacity, although they would be very welcome solutions if they have a good approach and someone implements them.

[Newsdee]

Do you know the proper timing values ​​for PCXT core (1280x200)? I had no problems with the other core 15khz.

Can you try if this build works better for you?
I could not fix the filters, but I managed to get the CGA resolution down to 640x200...
-

PCXT_CEtest2.rbf

(3.1 MiB) Downloaded 167 times

However, there is a part of this memory that is part of the text mode VRAM, and I use it to display the splash screen.

The splash screen has double the horizontal resolution of the CGA mode (e.g. after my change it's 1280x200).
Where is the code that draws its display? Maybe its clock needs adjusting.

[akeley]

I have finally got it going during the last week - big thanks to Newsdee & remax for help with that! The core is amazing, it's so great to have a proper speed for the early games, so kudos to spark2k06 and all the collaborators.

The 15kHz works natively, is scaled 1:1 and is the next best thing in this core, seeing as we need modelines for that in ao486. As dmckean says, 1280x200 is fine, it's a superresolution the likes of which we use all the time for 15kHz on MiSTer. There is a "but" though, seeing as on a PVM the DOS text displays fine, but once I start a game the image sort of fades away. Meanwhile, on my consumer CRT TV set it's okay. Might be something to do with sync, since they are handled differently on PVMs, or maybe something else with the signal. That's a minor snag to consider in the future though, since in general 15 kHz CGA is working, alongside all the colour modes (and looks really amazing).

IMG-20220720-105330.jpg (4.91 MiB) Viewed 5836 times

[wark91]

Do you know the proper timing values ​​for PCXT core (1280x200)? I had no problems with the other core 15khz.

Can you try if this build works better for you?
I could not fix the filters, but I managed to get the CGA resolution down to 640x200...
-
PCXT_CEtest2.rbf

However, there is a part of this memory that is part of the text mode VRAM, and I use it to display the splash screen.

The splash screen has double the horizontal resolution of the CGA mode (e.g. after my change it's 1280x200).
Where is the code that draws its display? Maybe its clock needs adjusting.

Working great ! the resolution is 640x200 at 15Khz.
The Splash Screen is now 1280x200 at 7.83 Khz. With this frequency, I think in most of the cases we needs to set "vsync_adjust=0" not to loose sync on the monitor.

[Newsdee]

The Splash Screen is now 1280x200 at 7.83 Khz. With this frequency, I think in most of the cases we needs to set "vsync_adjust=0" not to loose sync on the monitor.

I haven't yet found where the splash screen frequency is set, but it needs to change

[spark2k06]

The Splash Screen is now 1280x200 at 7.83 Khz. With this frequency, I think in most of the cases we needs to set "vsync_adjust=0" not to loose sync on the monitor.

I haven't yet found where the splash screen frequency is set, but it needs to change

Well, I'll tell you that even I don't know, it's something I've noticed, the fact that between splash screen and BIOS execution (when touching the CGA registers) the frequency changed, but it's something I had pending to discover... if you find something you'll let me know, tomorrow I'll check the RBF you've passed, but it looks very good

[Newsdee]

if you find something you'll let me know, tomorrow I'll check the RBF you've passed, but it looks very good

I got lucky sent you a PR so you can review the change

[akeley]

Can you try if this build works better for you?
I could not fix the filters, but I managed to get the CGA resolution down to 640x200...

I've tried your version but it acts the same as the prebeta 1.4 I've been using till now, ie the splash screen is out of sync and DOS looks fine. But it doesn't detect my hdd image (which works fine with prebetas), so I can't say if it solves the PVM display problem, which occurs only in games themselves.

But I doubt resolution change will affect anything, since it's already working fine on my consumer set @1280x200. PVMs should handle that easily too, they do for all other cores which use super resolutions (most of them). So I think the problem most likely lies somewhere else.

[suww37]

The Splash Screen is now 1280x200 at 7.83 Khz. With this frequency, I think in most of the cases we needs to set "vsync_adjust=0" not to loose sync on the monitor.

I haven't yet found where the splash screen frequency is set, but it needs to change

The screen is so crushedin 15khz sony pvm monitor. Is there a solution? Is timing the problem?

[kitune-san]

I added key code conversion for Tandy mode
However, I have not prepared an application that uses the cursor keys.
Could someone please try this core?

For the Tandy mode, would it be possible to map the backslash \ key to the \ key this would come in handy for those that don't have a full-size keyboard connected to their MiSTer? On the full-size keyboards in Tandy mode, the \ key is currently mapped to the 7 key on the number pad.

Just to add to this,

Code: Select all

`, ~, |, and \

are the ones that should be added and mapped. Everything else feels good.

Hmm..
It is possible to assign the ` and | keys, but difficult to assign the ~ and \ keys.
At first, I thought of a way to monitor the shift key and convert it to a ~ or \ key code when the shift + ` or | key is pressed.
In Tandy, however, the shift + ` or | key combination is assigned to the 8 or 7 key.
The converter needs to cancel the previously sent shift in some way, which cannot be solved with the current method.

If there is any available key, I will assign it there.

This is test rbf file.

[Newsdee]

The screen is so crushedin 15khz sony pvm monitor. Is there a solution? Is timing the problem?

Is this with my test build?

[Newsdee]

Well, I'll tell you that even I don't know, it's something I've noticed, the fact that between splash screen and BIOS execution (when touching the CGA registers) the frequency changed, but it's something I had pending to discover... if you find something you'll let me know, tomorrow I'll check the RBF you've passed, but it looks very good

Where did the splashscreen come from, originally? I tried to disable it (passing 0 to the Chipset module) but it still shows!
Whatever is initializing it has wrong clocks; it's only when it goes away that the clock becomes what we specify in the top module.

[dmckean]

I tested it with a 15khz sony pvm monitor. The top part shakes a lot and breaks. 1280X200 resolution is not normally output on crt monitors or TVs that support 15khz output.

If that's happening there are other problems with the timings. I have a groovemame setup and sometimes we use what's called "super resolutions" which are resolutions like 2560x240 which will work for many, many different arcade games and display perfectly fine on a 15khz monitor.

Do you know the proper timing values ​​for PCXT core (1280x200)? I had no problems with the other core 15khz.

No, it's something we have to make up on our own since it's not how the original hardware worked so you can't just measure it or something. MDA and CGA used a TTL interface to connect with the monitor. Having the DAC located in the monitor instead of on the graphics card allowed for the clear text modes that IBM PCs were famous for at the time.

[suww37]

The screen is so crushedin 15khz sony pvm monitor. Is there a solution? Is timing the problem?

Is this with my test build?

Not only does your bulid have this symptom, but other pcxt cores have the same symptom. I don't know why. There are no other arcade cores and console cores.

[spark2k06]

It is possible to assign the ` and | keys, but difficult to assign the ~ and \ keys.
At first, I thought of a way to monitor the shift key and convert it to a ~ or \ key code when the shift + ` or | key is pressed.
In Tandy, however, the shift + ` or | key combination is assigned to the 8 or 7 key.
The converter needs to cancel the previously sent shift in some way, which cannot be solved with the current method.

If there is any available key, I will assign it there.

This is test rbf file.

Thank you, in any case, it is already an improvement. If you want to send PR to the prebeta branch

[Newsdee]

Not only does your bulid have this symptom, but other pcxt cores have the same symptom.

Thanks. That tells me its not the resolution but something else. Maybe a sync issue. I don't yet fully understand how the core is handling video, but there is something non standard going on.

[somhi]

Where did the splashscreen come from, originally? I tried to disable it (passing 0 to the Chipset module) but it still shows!
Whatever is initializing it has wrong clocks; it's only when it goes away that the clock becomes what we specify in the top module.

The splash.hex is copied directly to the VRAM inside the VRAM module If I recall correctly. I also wanted to change resolution of the splash as in CGA mode it is not shown on screen if you remove all the MiSTer scaling stuff.
In my non-MiSTer ports this is why I start the core with MDA by default.

[spark2k06]

Where did the splashscreen come from, originally? I tried to disable it (passing 0 to the Chipset module) but it still shows!
Whatever is initializing it has wrong clocks; it's only when it goes away that the clock becomes what we specify in the top module.

The splash.hex is copied directly to the VRAM inside the VRAM module If I recall correctly. I also wanted to change resolution of the splash as in CGA mode it is not shown on screen if you remove all the MiSTer scaling stuff.
In my non-MiSTer ports this is why I start the core with MDA by default.

Issue resolved, the change in splash screen resolution was due to an error in the initial assignment of bit 0 of the CGA control register:

https://github.com/spark2k06/PCXT_MiSTe ... 04a1968c84

[suww37]

Where did the splashscreen come from, originally? I tried to disable it (passing 0 to the Chipset module) but it still shows!
Whatever is initializing it has wrong clocks; it's only when it goes away that the clock becomes what we specify in the top module.

The splash.hex is copied directly to the VRAM inside the VRAM module If I recall correctly. I also wanted to change resolution of the splash as in CGA mode it is not shown on screen if you remove all the MiSTer scaling stuff.
In my non-MiSTer ports this is why I start the core with MDA by default.

Issue resolved, the change in splash screen resolution was due to an error in the initial assignment of bit 0 of the CGA control register:

https://github.com/spark2k06/PCXT_MiSTe ... 04a1968c84

The prebeta pcxt core you upload does not recognize uart hdd. 2 pcxt beta 1.4 released to github is recognized.

[spark2k06]

The prebeta pcxt core you upload does not recognize uart hdd. 2 pcxt beta 1.4 released to github is recognized.

I also attach the experimental turbo version, with CPU speed selection from OSD. For the moment we keep it separate in an experimental branch, because with the latest SDRAM changes it loses cycle accuracy in normal mode at 4.77MHz. Also, if 4.77Mhz is selected in the experimental version in turbo mode, serdrive does not work at 460.8K, it must be lowered to 230.4K.

https://github.com/spark2k06/PCXT_MiSTe ... rebeta-1.5
https://github.com/spark2k06/PCXT_MiSTe ... -1.5-turbo

[suww37]

The prebeta pcxt core you upload does not recognize uart hdd. 2 pcxt beta 1.4 released to github is recognized.

I also attach the experimental turbo version, with CPU speed selection from OSD. For the moment we keep it separate in an experimental branch, because with the latest SDRAM changes it loses cycle accuracy in normal mode at 4.77MHz. Also, if 4.77Mhz is selected in the experimental version in turbo mode, serdrive does not work at 460.8K, it must be lowered to 230.4K.

https://github.com/spark2k06/PCXT_MiSTe ... rebeta-1.5
https://github.com/spark2k06/PCXT_MiSTe ... -1.5-turbo

I see. I got it well.

[suww37]

Not only does your bulid have this symptom, but other pcxt cores have the same symptom.

Thanks. That tells me its not the resolution but something else. Maybe a sync issue. I don't yet fully understand how the core is handling video, but there is something non standard going on.

Is it a sync problem? However, in other people's crt, 15khz is output normally, so I don't understand why I'm the only one who can't output it. Do you think there is a problem with the pcxt core? What kind of effort should I do to solve this? I'd like to see the 15khz crt screen.

[dmckean]

Not only does your bulid have this symptom, but other pcxt cores have the same symptom.

Thanks. That tells me its not the resolution but something else. Maybe a sync issue. I don't yet fully understand how the core is handling video, but there is something non standard going on.

Is it a sync problem? However, in other people's crt, 15khz is output normally, so I don't understand why I'm the only one who can't output it. Do you think there is a problem with the pcxt core? What kind of effort should I do to solve this? I'd like to see the 15khz crt screen.

Some CRTs are able to handle an off specification sync signal much better than others. In my experience so far on this project, it's normal for cores to have wonky video this early on. It's an early beta and you should just deal with it for now.

[Newsdee]

What kind of effort should I do to solve this? I'd like to see the 15khz crt screen.

I did not try it with the PCXT core, but in general my PVM requires the INI file to have composite_sync=1 to work well.
Maybe check if you have that on? If not, worth a try