In parallel with the MiSTer development I'm currently porting and updating the PCXT core to other non MiSTer FPGAS. The aim is to allow people who don't own a MiSTer to help in the development of the core, and port those improvements back to the MiSTer PCXT core.
Currently I'm maintaing at https://github.com/somhi/PCXT_DeMiSTify the following direct ports for:
- Altera Max 10 - DECA FPGA
- Altera Cyclone IV - NeptUNO FPGA
- Altera Cyclone V - SoCkit FPGA
The port is nearly the same for all three boards and is made with a fantastic tool called DeMiSTify to support porting MiST cores to other boards. Porting from MiSTer requires a more initial effort but after that porting to any FPGA supported by DeMiSTify is easy.
PCXT could be ported without too much effort to any Altera FPGA with SDRAM and enough BRAM resources to handle the core. Porting to Xilinx FPGAs would require more effort, as it seems all System Verilog code must be recoded to Verilog.
The main stopping factor to universalize the PCXT core is to move BIOS and VRAM into the SDRAM controller. Until that only a few FPGA boards can handle the core, while others would work but with reduced specs (e.g. DECA port cannot handle Tandy graphics as it can only fit 32 kB for CGA in BRAM). This is well explained by @spark2k06 in Saving BRAM To Facilitate Ports and New Developments thread.
I'm also maintaining a MiSTer compatible port for Cyclone V - SoCkit FPGA at https://github.com/sockitfpga/PCXT_SoCkit/
