Allwinner D1 Possible Future Cheaper FPGA Options

[CartoonDonkey]

[AngelicLiver]

Awesome work!

[Armakuni]

Is this really a viable solution ? The D1 is just a cheap RiscV based board too

Why not just fork the cores to the board he's using with the Cyclone, the Linux side is not needed.

[dmckean]

Is this really a viable solution ? The D1 is just a cheap RiscV based board too

Why not just fork the cores to the board he's using with the Cyclone, the Linux side is not needed.

The framework is the amazing part of MiSTer.

[Armakuni]

Isn't the framework mostly on the FPGA side though ?

The HPS is for mostly housekeeping duties

[zakk4223]

Isn't the framework mostly on the FPGA side though ?

The HPS is for mostly housekeeping duties

All rom loading/file browsing, usb controller interfacing/maping, configuration saving etc are handled by the HPS. The FPGA side framework is the scaler and some interfaces to sdram/ddr3. A lot of it is a bridge between the HPS and your core code.

You can get rid of the HPS, but you'll have to deal with a lot of stuff you normally wouldn't have to worry about. Or just lose the features entirely

[jca]

The framework is on the FPGA, on the HPS you have MISTer main which plays an essential role: all I/O (except screen) including a tight loop to handle controllers, loading cores, ... There is also Menu.rbf which is the startup core which among other things is used to the initial setup of a new controller

[dmckean]

I'm unaware of any other device that handles I/O as well as MiSTer. There's all sorts of potential for reusing that in other projects.

[hansfbaier]

My main goal is to have the MiSTer run on cheaper FPGA boards.
If, for example, I take this board https://www.aliexpress.com/item/4000170003461.html for $80
and a $16 Allwinner D1, then we have the basic hardware for less than $100
It still, of course would need a custom PCB to connect it all together, which I want to design,
but I am not sure of how much that would cost (maybe around $50 or so for small quantities, depending on what features it will have).
Using the QMTech form factor (like the NeptUNO does too), also has the advantage of using larger FPGAs, like the 200k Artix,
or the 325k Kintex, which both only cost around $100:
https://www.aliexpress.com/item/1005002960622091.html
https://www.aliexpress.com/item/1005003668804223.html
But, of course, all cores will need to be adapted, once a different FPGA is used.

Also, since yesterday, It can already load cores, see this video: https://www.youtube.com/watch?v=2uCWzgr ... e=youtu.be
It still has a lot of bugs, but I was quite pleased to get this far in a little more than one (intense) week.

[Armakuni]

Isn't the framework mostly on the FPGA side though ?

The HPS is for mostly housekeeping duties

All rom loading/file browsing, usb controller interfacing/maping, configuration saving etc are handled by the HPS. The FPGA side framework is the scaler and some interfaces to sdram/ddr3. A lot of it is a bridge between the HPS and your core code.

You can get rid of the HPS, but you'll have to deal with a lot of stuff you normally wouldn't have to worry about. Or just lose the features entirely

We have seen many other FPGA Multi Systems without a ARM side though MiST, Sidi, Neptuno, Turbo Chameleon etc

At least we haven't had the moaning MiSTer breaches GPL yet from this project like we have seen with other efforts in forking

[ericgus09]

My main goal is to have the MiSTer run on cheaper FPGA boards.

but I am not sure of how much that would cost (maybe around $50 or so for small quantities, depending on what features it will have).

This has always been what kills these kinds of efforts, when folks in the past over the years tried to find "cheaper" alternatives to the mister they end up finding it costs more to make (this is in part due to the fact the de10 nano is heavily subsidized by Intel, thats going to be hard to beat) .. I do wish you luck in your efforts, maybe you will be the lucky one that cracks this long standing nut.

[gregory003]

My main goal is to have the MiSTer run on cheaper FPGA boards.

but I am not sure of how much that would cost (maybe around $50 or so for small quantities, depending on what features it will have).

This has always been what kills these kinds of efforts, when folks in the past over the years tried to find "cheaper" alternatives to the mister they end up finding it costs more to make (this is in part due to the fact the de10 nano is heavily subsidized by Intel, thats going to be hard to beat) .. I do wish you luck in your efforts, maybe you will be the lucky one that cracks this long standing nut.

And where you found information that DE10 Nano is in any way donating by Intel? I could only find some academic discount worth few bucks. Any proof of that board is selling with loss on Intel side? I often see here people saying about Intel discount on De10, but no one has presented any proof.

As for the topic. I don't think porting Mister HPC framework gives you much. Cores still needs to be ported independently. And Mister framework was built strictly around features of DE10 and Cyclone V. Maybe would be better to starting from scratch, like OpenFPGA for Analogue Pocket.

[dmckean]

I doubt there's any subsidies beyond the education one. If you get prices quoted for the SOC used in the DE-10 nano in 10,000+ quantities in the Asian market it is much, much cheaper than small quantities in the North American market.

[rhester72]

I've been battling the "DE-10 subsidized by Intel" rumor for years. It's never, ever been true...but apparently that doesn't matter.

[ericgus09]

Well I can tell you there have been countless "lets build a cheaper Mister" in various incarnations and they all end the same way .. it costs more to build one no matter how much sincere effort they put in trying to find decent pricing on parts.. Honestly I wish you luck and do hope you succeed as it would open doors to even more people .. but many of us who have been here since pre-mister (mist) days, have seen this story play out over and over and over..

[dmckean]

The last time I even saw someone try was two years ago and in that time the price of the DE-10 Nano has gone up 100% and a lot of new FPGA hardware has come into the market. It's worth investigating what's possible.

Hardware has a life cycle too, normally somewhere around 7-10 years and the DE-10 Nano turned 5 last summer.

[ericgus09]

Hardware has a life cycle too, normally somewhere around 7-10 years and the DE-10 Nano turned 5 last summer.

Yea we raised this issue too when the Mister first became a thing..

[Armakuni]

My main goal is to have the MiSTer run on cheaper FPGA boards.

but I am not sure of how much that would cost (maybe around $50 or so for small quantities, depending on what features it will have).

This has always been what kills these kinds of efforts, when folks in the past over the years tried to find "cheaper" alternatives to the mister they end up finding it costs more to make (this is in part due to the fact the de10 nano is heavily subsidized by Intel, thats going to be hard to beat) .. I do wish you luck in your efforts, maybe you will be the lucky one that cracks this long standing nut.

And where you found information that DE10 Nano is in any way donating by Intel? I could only find some academic discount worth few bucks. Any proof of that board is selling with loss on Intel side? I often see here people saying about Intel discount on De10, but no one has presented any proof.

As for the topic. I don't think porting Mister HPC framework gives you much. Cores still needs to be ported independently. And Mister framework was built strictly around features of DE10 and Cyclone V. Maybe would be better to starting from scratch, like OpenFPGA for Analogue Pocket.

Doesn't the various branding from companies on the DE-10 give any hints how subsided the board is ?
It was developed for Intel's FPGA college program

FPGAs like the cyclone V are not necessarily expensive to produce as they are ten year old chips fabbed on TSMC 28nm but they are a niche product mostly for industrial use so carry high margins usually

[jd213]

My main goal is to have the MiSTer run on cheaper FPGA boards.

Looks like some major progress is being made on this going by your Twitter posts, I'm tempted to order some of these boards but I'll wait and see how things progress (plus I already have a MiSTer setup anyway, but always good to have a backup especially with current DE-10 Nano prices and availability)

[jca]

https://github.com/MiSTeX-devel

[gregory003]

My main goal is to have the MiSTer run on cheaper FPGA boards.

Interesting choice. That Kintex board have 256 MB built DDR3 RAM so we wouldn't need extra SD RAM module. Also 2x64 pin GPIO looks promising. We could have direct controller input in place of obviously missing SNAC, but digital/analog output board will be necessary. D1 nor Kintex board haven't any video output, but even if main/HPC board had any, sending video signal back to HPC RAM and next to GPU adds tons of lag (like Nvidia Optimus on some laptops does).

But I still have no idea why you opted for exotic, pretty expensive and exotic RISC-V board instead of easily accessible, cheap, well knowed Raspberry? Raspberry is also convenient choice due to MT32-Pi.

[grizzly]

DDR3 is way faster then SDRAM yes.
BUT DDR3 also has much higher latency then SDRAM, which could be a BIG deal with systems that was built using SDRAM.

And the DE-10 nano (also known as MiSTer ) has 1GB DDR3 that can not be used in many cores that needs the SDRam addon!

[Missus]

But I still have no idea why you opted for exotic, pretty expensive and exotic RISC-V board instead of easily accessible, cheap, well knowed Raspberry? Raspberry is also convenient choice due to MT32-Pi.

easily accessible, cheap, convenient... raspberry pi?
did you just time warp back to 2020?

[gregory003]

DDR3 is way faster then SDRAM yes.
BUT DDR3 also has much higher latency then SDRAM, which could be a BIG deal with systems that was built using SDRAM.

No, DDR3 hasn't higher latency than SD RAM. Where you get that information? Actually is opposite. Typical CAS latency for SD Ram at 133 MHz is 7.500 ns, for average DDR3 2133 MHz just below 0.500 ns. So…

EDIT: I screwed units…

And the DE-10 nano (also known as MiSTer ) has 1GB DDR3 that can not be used in many cores that needs the SDRam addon!

Because DDR3 on Cyclone V is managed by HPS and accessing it bring even more latency.

[german_user]

@hansfbaier
Cool to see, but for 50$ savings? I dont know if it worth that effort yet