Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

[spark2k06]

I am implementing an IDE-MMC(SDCard) conversion...

For DeMiSTify ports the soft controller already uses SD card. Usually we don't have a secondary SD card like MiSTer does.
For testing purposes can be added a secondary SD card, but in MiST / DeMiSTfiy should be used a more integrated way to deal with the IDE. Do you think It is still valid the code you pointed to me some posts above ?

I think the MiST framework has some method that allows it to emulate the SD operation, so that it is accessible from a VHD file, like MiSTer, although if I am not mistaken, it would emulate the SPI accesses.

The access that kitune-san has created is native, I don't think it would be complicated to adapt this SD emulation to the corresponding signals.

[kitune-san]

I made the following repo of my previous suggestions.
I have not been able to debug because I have not prepared a build environment and I do not have a development board. Sorry.

https://github.com/kitune-san/PCXT_DeMi ... suggestion

The following wires would be connected to data_io.

2023-02-28 230812.png (27.24 KiB) Viewed 7869 times

[somhi]

I made the following repo of my previous suggestions.
I have not been able to debug because I have not prepared a build environment and I do not have a development board. Sorry.

https://github.com/kitune-san/PCXT_DeMi ... suggestion

The following wires would be connected to data_io.
2023-02-28 230812.png

Thanks Kitune-san!
I've implemented it in this branch https://github.com/somhi/PCXT_DeMiSTify ... _demistify

As soon as I enable IDE in data_io ( data_io #(.ENABLE_IDE(1'b1)) data_io) the core does nothing, not even can do a reset. It gets hung in the splashcreen, so will need to debug it and ask for help in the MiST forums as well.

[somhi]

I made the following repo of my previous suggestions.
I have not been able to debug because I have not prepared a build environment and I do not have a development board. Sorry.

https://github.com/kitune-san/PCXT_DeMi ... suggestion

The following wires would be connected to data_io.
2023-02-28 230812.png

updated repository with latest changes needed by MiST firmware. Unfortunately the core gets stuck at splash screen don't know why.
deca_mist platform also uses same code as MiST and can be compiled in any latest Quartus.

need to add some more signals for SD access like SS4 and bidirectional DO. After that core boots but IDE is not detected yet in XT-IDE BIOS.

I'm using .FEATURES(32'h10) in user_io /* FEAT_IDE0_ATA */ https://github.com/mist-devel/mist-firm ... r_io.h#L81

Also changed clock of .hdd_clk ( clk_chipset ), //clk_cpu as recommended by slingshot (Another thing: use the same clock for data_io and ide modules as the chipset IDE controller)

[kitune-san]

Thanks for the information.
Next we will work on getting the waveforms and steadily correcting my errors.

• Check between xtbus-ide. trigger ide0_chipselect_n and see if data read/write is occurring.
• Check the hdd bus; monitor the hdd_* signal and see if any communication is occurring.

[kitune-san]

Thanks for the information.
Next we will work on getting the waveforms and steadily correcting my errors.

• Check between xtbus-ide. trigger ide0_chipselect_n and see if data read/write is occurring.
• Check the hdd bus; monitor the hdd_* signal and see if any communication is occurring.

Can you use SignalTap?
I have created a stp file. Please refer to it.

[kitune-san]

I forgot to push this commit yesterday.
The bus endianness may be the opposite of that of the Mister core.
https://github.com/kitune-san/PCXT_DeMi ... 84e8239149

[somhi]

Great, thanks. I'm hoping I could test it tomorrow.

[somhi]

Next we will work on getting the waveforms and steadily correcting my errors.

• Check between xtbus-ide. trigger ide0_chipselect_n and see if data read/write is occurring.
• Check the hdd bus; monitor the hdd_* signal and see if any communication is occurring.

This is happening when BIOS shows Master at 300h: not found
With your triggering conditions, I wasn't getting any trigger, so I've changed everything to Basic OR and don't care and just triggering with change of XT2IDE chip_select_n

ksnip_20230302-191650.png (165.3 KiB) Viewed 7608 times

hdd_data_rd, hdd_data_wr, hdd_wr, hdd_status_wr, hdd_cmd_req, hdd_dat_req never trigger (Basic OR)
same for hdd_data_in, hdd_data_out

I've already tried changing bus endianness but it does not work either.

[kitune-san]

I see that the core is not reading the status register.
The read pulses need to be corrected and the IDE module needs to be scrutinized.

[kitune-san]

Some fixes:
https://github.com/kitune-san/PCXT_DeMi ... 3082163256

• Enable primary channel master

• Disable secondary

  Code: Select all

          .hdd0_ena           (2'b11),     // enables Master & Slave drives on primary channel
          .hdd1_ena           (2'b00),     // enables Master & Slave drives on secondary channel
  

• Add read pulse delay

  Code: Select all

      always_ff @(posedge clock)
      begin
      	…
          ide0_read_edge          <= ide0_io_read   & ~prev_ide0_io_read;
      end
  

• Create buffer to store data read from ide.

  Code: Select all

      always_ff @(posedge clock)
      begin
          if (reset)
              ide0_data_bus_in <= 16'h0000;
          else if (ide0_read_edge)
              ide0_data_bus_in <= {ide0_drive_out[7:0], ide0_drive_out[15:8]};
          else
              ide0_data_bus_in <= ide0_data_bus_in;
      end
  

[somhi]

Some fixes:
https://github.com/kitune-san/PCXT_DeMi ... 3082163256

I can see barely a change in the waveforms (data_out and internal_data_bus)
Now it takes much longer than before to show the message "not found" after Master at 300h:
Follow waveforms at chip_select_n trigger:

ksnip_20230303-190636.png (175.43 KiB) Viewed 7454 times

Follow waveforms with manual trigger while waiting for the "not found" message:

ksnip_20230303-191157.png (174.28 KiB) Viewed 7454 times

hdd_data_rd, hdd_data_wr, hdd_wr, hdd_status_wr, hdd_cmd_req, hdd_dat_req, hdd_addr, and hdd_data_out never trigger (Basic OR)

io_write_n, memory_writte_n and ide0_writedata are changing at some point

hdd_data_in triggers continuously

ide_cs1fx, ide0_write_edge trigger at some point before the "not found" message":

ksnip_20230303-192712.png (174.24 KiB) Viewed 7445 times

[somhi]

some comments from slingshot over the MiST forum:

Is the BIOS writes to the IDE command register (1F7H)? If it does, then it should trigger bsy (hdd_cmd_req), and the ARM firmware, compiled with HDD Debug support should dump the task file registers.
If it doesn't write any commands, does it even check the status register (read 1F7H)?

[kitune-san]

Reading the status register seems to be working well.
0x50 means that the READY flag is up.

The XTIDE BIOS uses the Base (cmd block) address as 0x300.
This means that the command register is 0x307.

https://www.xtideuniversalbios.org/#Men ... ersubmenus

If you want to check if the command is actually written, you should trigger on the following condition.
ide0_address_1=7h or cpu_address=307h
ide_cs1fx=0h
io_write_n=0h

[kitune-san]

Are you using the same XTIDEBIOS as MiSTer?
BIOS ROMs created in the early stages of MiSTerPCXT development may not work properly because the settings do not match.

[somhi]

Are you using the same XTIDEBIOS as MiSTer?
BIOS ROMs created in the early stages of MiSTerPCXT development may not work properly because the settings do not match.

Well, I was sure that I updated the roms to those of MiSTer, but today I did a git pull on PCXT MiSTer repo and the ROM files have been updated.
Tried them, and now I got some progress!!! but not booting yet

photo_2023-03-05_19-26-35.jpg (199.93 KiB) Viewed 7248 times

[somhi]

After that I changed .hdd0_ena (2'b11), to .hdd0_ena (2'b10),
and now I'm getting not found again on both master and slave

Ok, changing to .hdd0_ena (2'b01), now it only detects Master

[somhi]

Reading the status register seems to be working well.
0x50 means that the READY flag is up.

The XTIDE BIOS uses the Base (cmd block) address as 0x300.
This means that the command register is 0x307.

https://www.xtideuniversalbios.org/#Men ... ersubmenus

If you want to check if the command is actually written, you should trigger on the following condition.
ide0_address_1=7h or cpu_address=307h
ide_cs1fx=0h
io_write_n=0h

ksnip_20230305-201005.png (172.76 KiB) Viewed 7225 times

[somhi]

After that I changed .hdd0_ena (2'b11), to .hdd0_ena (2'b10),
and now I'm getting not found again on both master and slave

From slingshot:
"If master and slave query gave the same results, that means that write to 0x306 is lost somewhere."

Debug info from MiST firmware https://atari-forum.com/viewtopic.php?p=444047#p444047

please check following post in atari forums, as there might important notes and more debug data valuable to you.
It has been checked that at least one sector is read and endianness is correct.

slingshot (Gyurco) :
"Why the BIOS reads this data first?
It doesn't look like a FAT Boot record or similar. Maybe the CHS-LBA translation by the firmware is not how the image file is created. Can the BIOS switched to use LBA mode?
However why doesn't it read the first sector (partition table?)

Or you can try to fdisk, format, sys to create a new disk which will use the firmware's idea of the geometry."

[kitune-san]

I can't see the image for some reason. (Permissions?
I think bios reads the first sector first.
We need to make sure the correct values are written to each register(drive, sector number, sector count, cylinder).

[somhi]

I can't see the image for some reason. (Permissions?
I think bios reads the first sector first.
We need to make sure the correct values are written to each register(drive, sector number, sector count, cylinder).

Don't know why you can't see the image. Try open image in a new tab. The image shows the trigger at the conditions you said so that is working.
have a look at https://atari-forum.com/viewtopic.php?p=444047#p444047 if you can see images also

The thing is that the first sector read is HDD: IDE0: read CHS, 0.2.1:126, 1
And that doesn't contains the boot sector, hence the "boot sector not found" message.

So that suggest to look at the questions arised by Slingshot from my latest post.

I would like to boot from disk A and format and transfer system to a new blank disk and see what happens, but don't think it won't be possible as for disk A I need a BIOS for serdrive and for MiST ide I need a different BIOS.

[somhi]

attached image from some posts above.

[kitune-san]

Don't know why you can't see the image. Try open image in a new tab. The image shows the trigger at the conditions you said so that is working.
have a look at https://atari-forum.com/viewtopic.php?p=444047#p444047 if you can see images also

I don't know why. It looks to me as follows. Do I need to register as a user?

2023-03-06 194451.png (90.79 KiB) Viewed 7046 times

[kitune-san]

Well, I am not the author of universalbios, so I can't say for sure, but I believe that if the BIOS is working right, it will read the boot sector first.
I suspect that the correct values are not being written to each register (drive, sector number, sector count, cylinder).
I am going to add each register to Signaltap.

[somhi]

Well, I am not the author of universalbios, so I can't say for sure, but I believe that if the BIOS is working right, it will read the boot sector first.
I suspect that the correct values are not being written to each register (drive, sector number, sector count, cylinder).
I am going to add each register to Signaltap.

Ok, good.

Regarding atari-forums, yes I cannot see images either if not logged with account.

[somhi]

I don't know why. It looks to me as follows. Do I need to register as a user?

Those are the relevant images from atari-forums:

getting SS4 low and some data:

ksnip_20230305-223529.png (347.34 KiB) Viewed 7010 times

You can try to dump only SS4, hdd_data_wr, hdd_data_out to see the whole transfer:

ksnip_20230305-225515.png (48.54 KiB) Viewed 7010 times

I have found the pattern from signaltap on the real image. Endianness is Ok.

ksnip_20230305-235651.png (129.75 KiB) Viewed 7010 times

[kitune-san]

Well, I am not the author of universalbios, so I can't say for sure, but I believe that if the BIOS is working right, it will read the boot sector first.
I suspect that the correct values are not being written to each register (drive, sector number, sector count, cylinder).
I am going to add each register to Signaltap.

Apparently the register file is a memory block and is difficult to monitor at all times.

I send STP files triggered by each write timing. Each file differs only in the trigger condition.
If the value of data_bus or tfr.data_a obtained at each trigger timing is not CHS=0/2/1 (is CHS=0/0/1), something is wrong somewhere.
If CHS = 0/2/1, hmmm, let's look at the BIOS code.
Please refer to this if you would like.

[kitune-san]

I am now trying to get waveforms under the same conditions with MiSTer, but it may be difficult to get waveforms with MIST where the registers are not visible.

[kitune-san]

In Mister, the boot sector readings(Read sector command (C4)) are as follows:

First_read.png (57.06 KiB) Viewed 6956 times

C = cylinder[15:0]=0
H = drv_addr[4:0]=0
S = sector[7:0]=1
As expected, CHS=0/0/1.

[kitune-san]

Well, I am not the author of universalbios, so I can't say for sure, but I believe that if the BIOS is working right, it will read the boot sector first.
I suspect that the correct values are not being written to each register (drive, sector number, sector count, cylinder).
I am going to add each register to Signaltap.

Apparently the register file is a memory block and is difficult to monitor at all times.

I send STP files triggered by each write timing. Each file differs only in the trigger condition.
If the value of data_bus or tfr.data_a obtained at each trigger timing is not CHS=0/2/1 (is CHS=0/0/1), something is wrong somewhere.
If CHS = 0/2/1, hmmm, let's look at the BIOS code.
Please refer to this if you would like.

I am now trying to get waveforms under the same conditions with MiSTer, but it may be difficult to get waveforms with MIST where the registers are not visible.

somhi

Is it possible to add the following code to IDE.v and see the signal with Signalap like MiSTer above?

Code: Select all

reg [7:0]   sector_number;
reg [7:0]   sector;
reg [15:0]  cylinder;
reg [7:0]   dev_head;

always @(posedge clk) begin
    sector_number   <= tfr[2];
    sector          <= tfr[3];
    cylinder        <= {tfr[5], tfr[4]};
    dev_head      <= tfr[6];
end