For the record, I spent some time trying to track the relevant ROMs and understand the changes. Here is what I found.
For the reference, here is the boot.rom file map pgimeno was able to create:
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Offs. Len. File name
00000 4000 GLUK661.ROM
04000 4000 TRDOS-5.04T
08000 4000 128p-0.rom
0C000 4000 128-1.rom
10000 4000 plus3-41-0.rom
14000 4000 plus3-41-1.rom
18000 4000 plus3-41-2.rom
1C000 4000 plus3-41-3.rom
20000 2000 plusd-patched.rom
22000 2000 plusd-sys.bin
24000 2000 MF128_36_3C.ROM
26000 2000 disasm.rom
28000 2000 mf3.rom
2A000 2000 zeros.bin
2C000 4000 48.rom
GLUCK661.ROM can be found on the author’s page, the actual ROM file name in the archive is glukpen.rom (it’s for Pentagon?). Source code is also available.
TR-DOS 5.04T seems to be an unofficial version which introduces some sort of “Turbo” format without modifying much else, so I assume it should be safe to replace it with 5.03 since we don’t really have real floppy drives and I doubt that “Turbo” format, which I presume is just a clever way to interleave sectors on disk, is going to speed up anything.
128p-0.rom and 128-1.rom can be found in many places (FUSE, for example). The interesting thing here is the use of the Pentagon’s first half.
+3 version 4.1 can also be found in many places. According to my experiments, it can be replaced with +3e, if necessary.
plusd ROM with a patch in an interesting beast, but I believe the “patch” is actually a dump error. The modification always forces “building bitmap at 0A6B” but all code belongs to “SCAN CATALOGUE SUBROUTINE”, so the modification is likely not needed. I think it should be safe to replace it with vanilla plusd.rom I think this modification is required, please see all details in the following post.
Now, plusd-sys.bin dump, is a modified version of the CONFIG2 code from the “MGT System Tape”. Three areas are modified, two appear to be dump errors. The actual functional change is the one related to screen selection when taking snapshot on 128:
SNP128_2 routine updated code:
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21BF: LD BC, #DFFE LD BC, DFBF ; poll keyboard row ?? Instead Y-P does DFBF port exist?
21C4: BIT 4,E -> BIT 7,E
21C6 JR Z, +17 -> JR NZ, +17 ; CHANGED
…
21CE: JR Z, +20 -> JR +20 ; SNP128_2
UPD 2023-05-30: Alright, I think I found mysterious port #DFBF. Comment says "read video page. available for MF128 and PlusD(patched)." So the screen page configuration is available via bit 7, and the code snippet makes sense.
I believe the following changes are safe to ignore.
SYSTEM VARIABLES block:
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ORIG NEW ID COMMENT
2003: 06 0C STPRAT "Steprate" 6 msec. (0C for MiSTer)
2008: 00 01 LFEED Number of line feeds after CR 1 ; default 1 no sure why CONFIG2 has 0 there, perhaps it’s updated by the BASIC programme
PRINTER CODES block, these definitely do not affect anything
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2012: 0d 1B INIT_PRT
2013: 80 40 INIT_PRT+1
201B: 4D 50 CHAR_PITCH+1
202B: 2a 4B GRAPH_DPI+1
202C: 05 80 GRAPH_DPI+2
The boot.rom section also contains something after 3a00 (that plusd-sys.bin is loaded at 2000), area which is not used by the known source. Perhaps a dump from a live system? it may be necessary to avoid +D initialisation from a disk.
Multiface 128 ROM is available here as MF128 vs.87.2.rom
disasm.rom is a funny creature. I think it’s a replacement for Multiface’s Genie debugger/disassembler. Disassembler this is actually the second half of the 16k ROM "Genie 128 Disassembler" available here.
Multiface 3 ROM available here as mf3 (kio-2006-07-13).rom
And, finally, 48 ROM is a regular, original, 48K rom available from many places.
Now, practical conclusion. It should be safe to replace almost all portions of the boot.com except the plusd-sys.bin. Based on the text above you should be able to take the CONFIG2 block and modify the code to handle screen snapshots for 128, but I am not sure about the code after 3a00. disasm.rom, well, anybody knows how to access it? Maybe it can be replaced with the original Genie disassembler. Disclaimer: I am not the core's developer, so this is my own conclusion based on the fact that all ROMs (except +D system code) are not modified in any way.
I am not good for any FPGA development work, so I cannot participate, sadly 
