CYC1000 / Handheld SNES FPGA Device?

[PikWik]

https://vhdplus.com/docs/components/cyc1000/

VOAYjO4.png (285.55 KiB) Viewed 8124 times

would a board with 25,000 logic elements be enough to port the MiSTer SNES core to the CYC1000?
could that conceivably be turned into a handheld SNES device (and possibly NES, genesis, PC engine).
thinking a 4" 4:3 screen with some decent d-pad/button rubbers (like an anbernic device)

i think this would be a great project for someone to make into a proper retro portable device.
would there be limitations with that board? or is there another board that would be better suited to do something like that?

[dshadoff]

This could work for some cores, but probably not snes.
I don’t see a separate CPU on that, so lots of I/O functions would need to be implemented in a soft CPU, stealing a large number of your LE’s. Might be possible to do one of the older arcade systems though (without video scaler, etc)

[softtest9]

There are a few fantasy consoles that might fit, like RISCBoy, icestation-32 or PicoStation 3D.

[jca]

This board can run a PDP11/70 with floating point and Ethernet. It can also replace the Pi in the PiDP11.
https://pdp2011.sytse.net/wordpress/pdp ... s/cyc1000/

[Newsdee]

The LEs are on par with MiST's Cyclone III. MiST uses an external ARM controller (48MHz ARM based IO controller with 256KBytes flash and 64 kBytes SRAM) and dedicated USB chip for modern controllers.

So if this board has enough pins it could theoretically be turned into a portable MiST with a little bit of extra hardware.

MiST has a SNES core, but with some limitations to save FPGA space (e.g. no super FX)

[PikWik]

hmmm, i would be OK with that.

im mostly looking for a way to play portable SNES in FPGA (with any extra cores being a plus). i think someone could design a simple PCB that could add an ARM controller, a USB, and have everything sit flat enough to put a battery/buttons/screen in a thin shell

[Newsdee]

Looks like there are some cores already ported to it...
No SNES yet, though:
https://github.com/AtlasFPGA/Binaries-CYC1000

[subcritical]

If you desired that's the interactive bill of materials BOM of the ATLAS MINI.

interactive_bom_atlas_mini.html.zip

(297.32 KiB) Downloaded 149 times

The object was to get as much pins free, and use bus standards, like the 2x20 Rasberry Pi GPIO.
The are some similarities with the cyclone III used in the MIST, the CYC1000 has the same 66 9Kbits blocks, and the same amount of KLES 25KLes.
The key point is that cyclone 10 LP is most a Cyclone IV with the drawn current limited in their pins, the PLLs are the same between Cyclone IV & Cyclone 10 LP, only improves a bit further over the ones in the Cyclone III family.
Nowadays there are used more than three ways of video to see the cores, composite, vga222, scart232 and DIGITAL-VIDEO with or without sound.
Also some developers used I2S boards conected to the pins in the 2x20 bus.
The DIGITAL-VIDEO wrappers are direct, so no framebuffer or framescaller, that's force to move the board until you can reach a monitor that could see the DIGITAL-VIDEO signal, some times a monitor that has VGA as one of their posible inputs, those monitors should support further more resolutions an frequencies, to have such a monitor, capable of seeing a DVI signal is most related to a case of luck.
One key aspects in the future is that CYC1000 has another CLK input signal.
The platform is more focussed in learning HDL languages.

We have also a little group of people arround this microFPGA in Telegram.

[subcritical]

One of the characteristics of the CYC1000 is that it has 2 clocks, one as standard, a 12Mhz oscillator from the manufacturer mems, with which we adjust the frequencies in the PLLs, and a second clock where I have a PAL clock set (28,35716Mhz), this oscilator is currently replaced by an SI5351 governed from a microcontroller.

The frequencies without a PAL oscillator generate many visual artifacts, once the (Minimig UnAMIGA) implementation is recompiled with the required 28.37516Mhz oscillator located in CYC10000'S PIN_E15, The PAL frequency has been used since the first Minimig by Dennis Van Weeren's.

The vast majority of artifacts disappear with the PAL oscilator located in PIN_E15 with the exact frequency(28,35716Mhz).

It is a serious problem in the following families, Cyclone 10 LP, and Cyclone IV. Families that share the same type of PLLs

In the MiSTER when using the description of a Minimig in a Cyclone V, the frequency approximation is almost perfect due to Cyclone's V PLLs .

In the following video you can see how bad is the UnAMIGA approximation from a 50Mhz oscillator, because 28,5714285714Mhz, it is not the needed PAL frequency.
https://www.youtube.com/watch?v=_fdW82q ... Ni&index=2

PAL=28,35716Mhz
UnAMIGA=28,5714285714Mhz

So i create a podcast to fix the UnAMIGA, providing to the UnAMIGA community with the most essential, correct starting frequency for the implementation of (Minimig UnAMIGA).