Reference for all DE10-nano DIP switches

[egrath]

Hi,

there are a total of 10 DIP switches (6 small sized ones, 4 big ones) on the DE10-nano board. There is also plenty of information on how to set these switches for correct operation.

However, is there a reference on what all of those switches actually do?

What I found out so far:

Big DIP array
Big SW 0 ON = Has something to do with MiSTercade JAMMA board
Big SW 2 ON = Disable 24 Bit DAC for I/O boards that don't have a 24 Bit DAC (Reference: JAMMIX Operators Guide, https://drive.google.com/file/d/16IC4hA ... hXbWRLG9xE)
Big SW 3 ON = Enable Dual SDRAM (Reference: https://misterfpga.co.uk/dual-sdram-mister-fpga/)

Small DIP array
Small SW1-5: Used by the DE10-nano itself to configure if the FPGA is being programmed by some internal serial flash chip on power up (EPCS mode) or by the host operating system (HPS mode). MiSTer uses the later on, so it should be in the following position:

Small SW1 ON
Small SW2 OFF
Small SW3 ON
Small SW4 OFF
Small SW5 ON
Small SW6 Is marked as N/A in the DE10-nano manual, seems like it's not used right now for anything, but keep it set to ON

Reference: https://www.mouser.com/datasheet/2/598/ ... 108056.pdf (Table 3.2)

With kind regards,
Egon

[FPGA64]

The 6 Small ones configure the FPGA even the Docs from Intel are vague on what they do. They basically just show the correct setup and never explain what they do. With this in mind its best to never change them from the default values suggested.

[egrath]

The 6 Small ones configure the FPGA even the Docs from Intel are vague on what they do. They basically just show the correct setup and never explain what they do. With this in mind its best to never change them from the default values suggested.

Thank you, took a look into the manual (stupid me not doing this earlier ...) and updated the post above