DE25-Standard Terasic Inc Press release

[seastalker]

Saw this update from Terasic and re-posting here.

MORE INFO HERE:
https://www.terasic.com.tw/cgi-bin/page ... =1#section

DE25-Standard - The newest generation dev. kit for Altera® University Program!

Designed to address the applications requirements for embedded systems, robotics, and digital logics, the DE25-Standard development kit takes advantage of the Altera® Agilex™ 5 FPGA with 138K LEs to offer larger FPGA capacity and advanced feature sets such as 1GB DDR4 32-bit data bus, 64MB SDRAM, 8-channel ADC header, GPIO header, an HSMC high-speed connector, and black and light mini LCD, etc. A rich set of input and output features, such as robust switches, LEDs, seven-segment displays, and commonly-used I/O interfaces are included to meet the needs of teaching and experiments.

In addition, the DE25-Standard is armed with the advanced HDMI output port (1080P), a two-lane MIPI CSI /DSI connector for camera and display, and a composite RCA jack for surveillance camera. Developers can leverage the AI tensor block on the Agilex™ 5 FPGA, the MIPI CSI/DSI connector, HDMI output, and the composite RCA jack on the DE25-Standard to develop AI-related applications such as video processing and computer vision.

Key Benefits:

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Altera® Agilex™ 5 E-Series FPGA with 138K logic elements. Core speed grade: -4S
Support Nios® V soft processor based on the RISC-V instruction set architecture
1GB DDR4 SDRAM (32-bit data bus) and 64MB SDRAM
Full HD HDMI output and one 2-lanes MIPI connector for camera/display
HSMC/2x20 DE-GPIO/1x6 GPIO connector for I/O expansion
HPS communication interface with USB to UART, MicroSD socket and Gigabit PHY, and two USB host ports
8-channel ADC input and accelerometer
Support Linux BSP and RTL example designs for on-board memory and peripherals

Important Notice:

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DE25-Standard sample board is available now!
DE25-Standard sample board is built with Agilex™ 5 FPGA with 656K LEs (A5ED065BB32AE4SR0) as the production FPGA selected for this dev. kit is 
not yet released by Altera. Standard production board will be built with Agilex™ 5 FPGA with 138K LEs (A5ED013BB32AE4S).

[Chris23235]

Some of the features like the b/w display and the already on board SD-RAM make me think if the people at Terasic had the MiSTer project at least in the back of their mind designing the board.

[thorr]

Some comparison with the DE10-nano

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DE25-Standard-  FPGA: A5ED013BB32AE4S (138K LEs)
DE10-Nano-        Intel Cyclone® V SE 5CSEBA6U23I7  device (110K LEs)
DE25-Standard-  DDR4: 1GB DDR4 with 32-bit data bus (no ECC), shared with FPGA and HPS sides
DE10-Nano-        1GB DDR3 SDRAM (32-bit data bus), shared with FPGA and HPS sides
DE25-Standard-  SDRAM: 64MB SDRAM with 32-bit data bus (no ECC).
DE25-Standard-  HDMI 2.0 Output Port (Support 1080P)
DE10-Nano-        HDMI TX, compatible with DVI 1.0 and HDCP v1.4

The DE10-Standard is $499, so this won't be cheap probably.

[rickdangerous]

Some of the features like the b/w display and the already on board SD-RAM make me think if the people at Terasic had the MiSTer project at least in the back of their mind designing the board.

Of course they have.

[zakk4223]

Some of the features like the b/w display and the already on board SD-RAM make me think if the people at Terasic had the MiSTer project at least in the back of their mind designing the board.

No, the de-10 standard also had these things. It's basically the de-10 standard upgraded to the new FPGA

[mike911]

Some more info from the user manual vs de10 nano: 138k LE vs 110k LE, 25% more. Dual a55 + dual a76 up from dual core A9, 1gb ddr4 1200mhz instead of ddr3 400mhz, 8.42 Mbits of embedded memory vs 5,570 Kbits. Seems to be a good upgrade, if a de25 nano arrives as a replacement for the de10 nano, we might have a Mister2 board candidate.

[rickdangerous]

You can expect that by Q4 2025 or Q1 2026. The plan is have a very similar form factor and will be MiSTer friendly.

[pgimeno]

DE25-Standard- DDR4: 1GB DDR4 with 32-bit data bus (no ECC), shared with FPGA and HPS sides
DE10-Nano- 1GB DDR3 SDRAM (32-bit data bus) - HPS side only

Are you sure? I thought that's the RAM used by the cores that don't need SDRAM.

[thorr]

DE25-Standard- DDR4: 1GB DDR4 with 32-bit data bus (no ECC), shared with FPGA and HPS sides
DE10-Nano- 1GB DDR3 SDRAM (32-bit data bus) - HPS side only

Are you sure? I thought that's the RAM used by the cores that don't need SDRAM.

I am not sure. I got this from the specifications of each product on the website. The 1GB DDR3 was only listed in the HPS section for the DE10-Nano, and the 1GB DDR4 was listed in both sections for the DE25-Standard and both sections stated that it was shared.

[zakk4223]

DDR3 is shared on the Nano too

[thorr]

Thanks, I will edit my post.

[seastalker]

This offer from Terasic may interest developers!!!

Be the pilot user for the new DE25-Standard Development Kit! Write a technical review!
https://mail.terasic.com.tw/epaper/2024 ... eview.html

The article includes:

Your Job:

Write a technical review article for the DE25-Standard development kit!

Event Timeframe:

8/21 - 8/26: Submit your application online
8/30: Announce the selected reviewers and ship out the boards
9/30: Submit your final review article
10/1: Terasic will start to publish your review after October 1

Rewards:

A free DE25-Standard Development Kit
$700 Terasic Coupon
A Certificate of Excellence for contribution to Altera® University Program

[dshadoff]

Wow, that's a huge heatsink and fan on that board - I'm pretty sure that wasn't on the last picture I saw of this board...

[trumpetlicks]

As there is talk about a new FPGA board for a potential new MiSTer version, has anyone looked at the Xilinx Kria K26 (Kria KV260 Vision AI Starter Kit)?
https://www.cnx-software.com/2021/04/28 ... pga-mpsoc/
https://www.amd.com/en/products/system- ... tarter-kit

It is also a "starter kit" board, but with an ARM HP system comprised of:

• Quad A53 @ (up to) 1.5 GHz (1333MHz after delving into docs)
• Dual-core Arm Cortex-R5F real-time processor up to 600MHz (Probably actually better for the MT-32 side of things, 550MHz after delving into docs)
• 4GB DDR4

The logic fabric is comprised of:

• 256K logic cells (I'd Have to dig into the clocking capability/speed)
• 1,248 DSP slices
• 26.6Mb On-Chip SRAM

The one thing I don't see is the 64MB of SDRAM, although I believe there is enough High Speed IO coming off the chip and out to accessible pins that a (more) custom interface board would be able to add it!

AND this board goes for around $250 (power supply separate)

[werpu]

The arm part sounds interesting, this could move the mt32pi project into full software mt32 emulation on the mister without the need for a pi!

[pomegran]

I am awaiting a board with far more LEs allowing us to take us to the next step of PS2, Dreamcast, GameCube etc. While this is an upgrade, it's not much bigger than the DE-10 which I must say is an incredible piece of kit running up to 5th generation machines.

PS2 etc. in FPGA world be incredible, and I'm happy to wait and pay more as and when that happens.

[MostroW]

I am awaiting a board with far more LEs allowing us to take us to the next step of PS2, Dreamcast, GameCube etc. While this is an upgrade, it's not much bigger than the DE-10 which I must say is an incredible piece of kit running up to 5th generation machines.

PS2 etc. in FPGA world be incredible, and I'm happy to wait and pay more as and when that happens.

If that would ever happen i would have no qualms shelling out € 800 for a board that offers that kind of possibilities.
However that would also be the last generation of consoles i'd be playing, everything else is practically available on PC platform.

[rhester72]

I am awaiting a board with far more LEs allowing us to take us to the next step of PS2, Dreamcast, GameCube etc. While this is an upgrade, it's not much bigger than the DE-10 which I must say is an incredible piece of kit running up to 5th generation machines.

PS2 etc. in FPGA world be incredible, and I'm happy to wait and pay more as and when that happens.

It's not just about LEs, it's also about gate switching speed and design complexity. You'd be paying a LOT more, and I doubt most if any of those systems will be recreated in FPGA in our lifetimes.

[FoxbatStargazer]

The arm part sounds interesting, this could move the mt32pi project into full software mt32 emulation on the mister without the need for a pi!

This is a funny turn of phrase, on-device MUNT and Fluidsynth are already installed on Mister and semi-usable, just slotting in a more powerful ARM should make them more reliable.

[pomegran]

I am awaiting a board with far more LEs allowing us to take us to the next step of PS2, Dreamcast, GameCube etc. While this is an upgrade, it's not much bigger than the DE-10 which I must say is an incredible piece of kit running up to 5th generation machines.

PS2 etc. in FPGA world be incredible, and I'm happy to wait and pay more as and when that happens.

It's not just about LEs, it's also about gate switching speed and design complexity. You'd be paying a LOT more, and I doubt most if any of those systems will be recreated in FPGA in our lifetimes.

Really? PS2 not in our lifetimes? I'm not 90

I really do hope you're wrong.

[werpu]

The arm part sounds interesting, this could move the mt32pi project into full software mt32 emulation on the mister without the need for a pi!

This is a funny turn of phrase, on-device MUNT and Fluidsynth are already installed on Mister and semi-usable, just slotting in a more powerful ARM should make them more reliable.

Thats exactly the point atm, on a pure MiSTer installation they are semi usable aka they fail in many games with skips and timing issues, hence the offloading of munt and fluidsynth onto an external PI, by having a faster ARM this wont be necessary anymore!

[Lowe0]

The arm part sounds interesting, this could move the mt32pi project into full software mt32 emulation on the mister without the need for a pi!

This is a funny turn of phrase, on-device MUNT and Fluidsynth are already installed on Mister and semi-usable, just slotting in a more powerful ARM should make them more reliable.

Thats exactly the point atm, on a pure MiSTer installation they are semi usable aka they fail in many games with skips and timing issues, hence the offloading of munt and fluidsynth onto an external PI, by having a faster ARM this wont be necessary anymore!

I’d rather see a carrier board that accepts a Dreamblaster than use FluidSynth. The hardware is too good, and too affordable, to go back to software.

[Neocaron]

When the arm is overclocked Munt/Fluidsynth are working very very well on the Mister, especially for something that doesn't need extra hardware.

[rhester72]

When the arm is overclocked Munt/Fluidsynth are working very very well on the Mister, especially for something that doesn't need extra hardware.

In my experience, even when overclocked, stutter and buffer overrun was pretty common. The user port add-on modules work like butter, though.

[GradiusV]

Atum A5 would be the real future, however is too expensive: $2850

Agilex 5 SoC FPGA with 656K LEs:
https://www.terasic.com.tw/cgi-bin/page ... sh&No=1342

[german_user]

DE25 nano with above FPGA (DE25-Standard) make only sense if DE10 (or clones) is EOL. The Specs are not a huge step compared to DE10. I believe a DC core would also hard to develop on this version of the fpga. Terasic links above shows HDMI 1.4 only, so here is on the paper no advantage visible. For me it seems that the HPS side is improved. I dont know the possible clockrates yet, but the le count is only a small upgrade.

[dshadoff]

According to their documents, the internal fabric will be significantly faster, there is more internal BRAM, and the LEs are likely not the same - they may be more capable. Plus, the ARM side is SIGNIFICANTLY more powerful (more cores, higher clock frequency).

But all of this is academic until they actually release the devices, and somebody uses the toolchain to build an existing core for comparison purposes.
Who knows - maybe the "fitter" (part of compile tool) will also be able to make use of more cores when compiling the bitstreams for this device when it comes out.

[niallquinn]

Same 64meg SDRAM as we have now, it doesn't matter that it's got more logic cells, but we'd still have the same problems why some cores aren't possible as we do now, according to one of the Devs on Discord.

[dshadoff]

Depends which cores (I am one of the devs on discord too).

Current FPGA: can do most consoles and arcades up to about 1993-ish.

DE25: Can probably buy another few years of dev due to increased clocks and more internal BRAM. Faster/more cores of ARM can probably support some more system functionality and faster HPS<->core communication. ao486, Jaguar will clearly benefit. Additional 1992-1996 system development would become less difficult, as the constraints are generally: a) internal BRAM memory, b) clock frequency limits for meeting closure, c) bandwidth to external memory (i.e. multiple buses), and lastly d) size of design versus target FPGA.
Any core which needs a "cherry-picked" build which meets timing closure (there are several) would definitely benefit.

Dreamcast and beyond are still unlikely on a <200K LE FPGA, and devs are less enthusiastic about framebuffer-based systems in the first place, as the gap between FPGA and other emulation becomes diminished.

So, is it worth it ? Depends what you think is needed.

[niallquinn]

Depends which cores (I am one of the devs on discord too).

Current FPGA: can do most consoles and arcades up to about 1993-ish.

DE25: Can probably buy another few years of dev due to increased clocks and more internal BRAM. Faster/more cores of ARM can probably support some more system functionality and faster HPS<->core communication. ao486, Jaguar will clearly benefit. Additional 1992-1996 system development would become less difficult, as the constraints are generally: a) internal BRAM memory, b) clock frequency limits for meeting closure, c) bandwidth to external memory (i.e. multiple buses), and lastly d) size of design versus target FPGA.
Any core which needs a "cherry-picked" build which meets timing closure (there are several) would definitely benefit.

Dreamcast and beyond are still unlikely on a <200K LE FPGA, and devs are less enthusiastic about framebuffer-based systems in the first place, as the gap between FPGA and other emulation becomes diminished.

So, is it worth it ? Depends what you think is needed.

Thanks for that, also it depends on the price when it's on sale widely, if it's say £200-300 okay. If it's double that, possibily not worth it.
Faster cores such as the AO486, might be nice, but we're unlikely to get to a Pentium 1 P60, or are we???