Lets actually try Hybrid Emulation

[rhester72]

It was a pipedream to start with that would produce little benefit at enormous effort required if even possible to do so in a stable fashion (which it never was).

[Neocaron]

Not to be rude, but terms like 'Impossible' and 'pipe dream' always age poorly in the context of the MisterFPGA project. So, I'd refrain from being categorical on this topic too. Even if it's not used here, it might be developed for another project. Nothing is useless in the end.

[rhester72]

I provided the very technical justifications for my position on this in this very thread years ago. They remain as true now as they were then.

[lordoftime79]

sorry about the necro bump but i finally managed to get this working but i was seeing really lack luster speeds - it turns out i was using the older files and the links for the later ones are all dead - now while i appreciate this is probably abandoned if anybody has the later itterations of this can you please upload them somewhere for me to use? thank you.

[lordoftime79]

anyone? i just wanted to push this back to the top as i could use those files - i have checked wayback machine/archive.org but no luck.

[lordoftime79]

i have just copied the set up from my test sd card that was working fine to my up to date sd card and now i dont get the arm cpu option - can anybody help please?

[foft]

Been a while but pretty sure I put all the binaries and code on GitHub.

Think this repo has binaries:
https://github.com/scrameta/MiSTer_Hybrid_Support

[foft]

Several years later...

Came across this page talking about using the FPGA->HPS SDRAM bridge:
https://people.ece.cornell.edu/land/cou ... index.html

This performs much better but its FPGA->RAM on the HPS side, but its not a request/response to a memory mapped address from HPS.

So the idea would be:
i) Amiga chipset access memory on the HPS side using this bridge. i.e. move the memory to HPS side.
ii) Only use the slow HPS->FPGA bridge to access the hardware registers.

Edit: Oh I see I was already considering this before, but never implemented it.

[LamerDeluxe]

Several years later...

Came across this page talking about using the FPGA->HPS SDRAM bridge:
https://people.ece.cornell.edu/land/cou ... index.html

This performs much better but its FPGA->RAM on the HPS side, but its not a request/response to a memory mapped address from HPS.

So the idea would be:
i) Amiga chipset access memory on the HPS side using this bridge. i.e. move the memory to HPS side.
ii) Only use the slow HPS->FPGA bridge to access the hardware registers.

Edit: Oh I see I was already considering this before, but never implemented it.

Would this be very complicated to implement in the current core?

[foft]

Would this be very complicated to implement in the current core?

Good question, not sure. I was hoping one of the main core developers would chime in

I'll probably have a look at some point. Threw my back out shortly after posting this so not done much hobby stuff lately...

[Neocaron]

I like to see this topic still alive! Sad to see you hurt yourself foft, get better quickly!

[LamerDeluxe]

Would this be very complicated to implement in the current core?

Good question, not sure. I was hoping one of the main core developers would chime in

I'll probably have a look at some point. Threw my back out shortly after posting this so not done much hobby stuff lately...

Ouch, sorry to hear that, take your time, backs can be a real hassle.

[FPGA64]

Isnt that paper about the DE 1 and we have a DE 10 in the Mister

[smarkusg]

Hello
As this is my first message on the forum - welcome to the forum.
I am a recent owner of a MiSTER Pi.

@lordoftime79
I have recompiled with the patch from @foft : Mister, the current minimig and kernel modules and qemu.
It all runs under the current version of Mister.
I don't know about code changes under fpga unfortunately and everything works as previous versions.
Would probably have to make changes @foft.
If you need to run core hybrid further let me know.

[smarkusg]

I found an interesting message about hybrid emulation.
(FPGA + Emu68 JIT on Pi4/3). Tang Nano 20k board and probably MiSTeX.
The sysinfo result is interesting

https://x.com/Claude1079/status/1878319 ... u6GxQ&s=19