MiSTer FPGA Forum

spark2k06 wrote: ↑Sat May 28, 2022 1:08 pm
Because they originally carry the 'n', I understand that they work in reverse, 1 = disabled and 0 = enabled. Since the KFPC-XT signals do not, I assumed that they had to be negated.

kitune-san wrote: ↑Sat May 28, 2022 4:26 pm A bug was found in RAM.sv of KFPC-XT.
The RAM access range was 00000h-9FFFFFh, but it was 00000h-7FFFFFh.
An error may have occurred when accessing 80000h-9FFFFFh.

https://github.com/kitune-san/KFPC-XT/c ... 4cfde55893

spark2k06 wrote: ↑Sat May 28, 2022 10:11 am Thank you both, I will take your advice into account. On another note, I have tried to add the SDRAM signals to have 640KB + HMA available initially:

pgimeno wrote: ↑Sat May 28, 2022 11:38 pm

spark2k06 wrote: ↑Sat May 28, 2022 10:11 am Thank you both, I will take your advice into account. On another note, I have tried to add the SDRAM signals to have 640KB + HMA available initially:

HMA?

That's an AT thing, not an XT thing.

kitune-san wrote: ↑Sun May 29, 2022 8:15 am The following changes are being considered.
https://github.com/kitune-san/KFPC-XT/c ... 17e7ffd6c7

RAM.sv and KFSDRAM.sv works in my DE0-CV.

spark2k06 wrote: ↑Sun May 29, 2022 9:48 am

kitune-san wrote: ↑Sun May 29, 2022 8:15 am The following changes are being considered.
https://github.com/kitune-san/KFPC-XT/c ... 17e7ffd6c7

RAM.sv and KFSDRAM.sv works in my DE0-CV.

It still doesn't work, I update your changes in the specific branch to address this issue:

https://github.com/spark2k06/PCXT_MiSTe ... sdram-test

Don't worry, you've already done enough in this regard, we'll find the cause at some point

It must be something specific to the signal configuration of the MiSTer.

kitune-san wrote: ↑Sun May 29, 2022 11:27 am
Oh...
Can the SDRAM I/O Standard be changed to 3.3V LVTTL?
That's all I can come up with now.

;-------------------------------------------------------------------------
; Test first 32 KiB (MIN_RAM_SIZE) of RAM

	mov	al,e_low_ram_test
	out	post_reg,al
	xor	si,si
	xor	di,di
	mov	ds,di
	mov	es,di
	mov	dx,word [warm_boot+biosdseg*16] ; save soft reset flag to DX
	mov	ax,55AAh		; first test pattern
	mov	cx,MIN_RAM_SIZE*512	; RAM size to test in words
    rep	stosw				; store test pattern
	mov	cx,MIN_RAM_SIZE*512	; RAM size to test in words
.1:
	lodsw
	cmp	ax,55AAh		; compare to the test pattern
	jne	low_ram_fail
	loop	.1
	xor	si,si
	xor	di,di
	mov	ax,0AA55h		; second test pattern
	mov	cx,MIN_RAM_SIZE*512	; RAM size to test in words
    rep stosw				; store test pattern
	mov	cx,MIN_RAM_SIZE*512	; RAM size to test in words
.2:
	lodsw
	cmp	ax,0AA55h		; compare to the test pattern
	jne	low_ram_fail
	loop	.2
	xor	di,di
	xor	ax,ax			; zero
	mov	cx,MIN_RAM_SIZE*512	; RAM size to test in words
    rep stosw				; zero the memory
	jmp	low_ram_ok		; test passed

low_ram_fail:
	mov	al,e_low_ram_fail	; test failed
	out	post_reg,al

;-------------------------------------------------------------------------
;  Low memory error: beep - pause - beep - pause ... - 400 Hz

	mov	al,0B6h
	out	pit_ctl_reg,al		; PIT - channel 2 mode 3
	mov	ax,pic_freq/400		; 400 Hz signal
	out	pit_ch2_reg,al
	mov	al,ah
	out	pit_ch2_reg,al
	in	al,ppi_pb_reg
.1:
	or	al,3			; turn speaker on and enable
	out	ppi_pb_reg,al		; PIT channel 2 to speaker
	mov	cx,0
.2:
	nop
	loop	.2
	and	al,0FCh			; turn of speaker
	out	ppi_pb_reg,al
	mov	cx,0
.3:
	nop
	loop	.3
	jmp	.1

spark2k06 wrote: ↑Sun May 29, 2022 9:48 am It still doesn't work, I update your changes in the specific branch to address this issue:

https://github.com/spark2k06/PCXT_MiSTe ... sdram-test

Don't worry, you've already done enough in this regard, we'll find the cause at some point

It must be something specific to the signal configuration of the MiSTer.

	assign SDRAM_nCS = ~SDRAM_CS;
	assign SDRAM_nCAS = ~SDRAM_CAS;
	assign SDRAM_nRAS = ~SDRAM_RAS;
	assign SDRAM_nWE = ~SDRAM_WE;

	assign SDRAM_nCS = SDRAM_CS;
	assign SDRAM_nCAS = SDRAM_CAS;
	assign SDRAM_nRAS = SDRAM_RAS;
	assign SDRAM_nWE = SDRAM_WE;

kitune-san wrote: ↑Sun May 29, 2022 2:33 pm
Have you changed any of the following？

Code: Select all

	assign SDRAM_nCS = ~SDRAM_CS;
	assign SDRAM_nCAS = ~SDRAM_CAS;
	assign SDRAM_nRAS = ~SDRAM_RAS;
	assign SDRAM_nWE = ~SDRAM_WE;

Inversion is not necessary.

Code: Select all

	assign SDRAM_nCS = SDRAM_CS;
	assign SDRAM_nCAS = SDRAM_CAS;
	assign SDRAM_nRAS = SDRAM_RAS;
	assign SDRAM_nWE = SDRAM_WE;

spark2k06 wrote: ↑Sun May 29, 2022 5:07 pm @pgimeno, do you know any debugger that doesn't require DOS functions? That works without any problem only with the BIOS functions? One that can load in memory without problems.

spark2k06 wrote: ↑Sun May 29, 2022 2:45 pm What I am not so sure about is this:

Code: Select all

assign SDRAM_DQ_IN = SDRAM_DQ;
assign SDRAM_DQ = ~SDRAM_DQ_IO ? SDRAM_DQ_OUT : 16'hZZ;

kitune-san wrote: ↑Sun May 29, 2022 11:37 pm
It is necessary to ensure that the two outputs do not collide.

16'hzzzz" is more accurate than "16'hzz".

kitune-san wrote: ↑Sun May 29, 2022 11:38 pm Could you please show me your latest SDC file?

spark2k06 wrote: ↑Mon May 30, 2022 4:22 am How do I regenerate those files from Quartus, because starting from a new compilation, they are not updated...

kitune-san wrote: ↑Sun May 29, 2022 11:38 pm Could you please show me your latest SDC file?

kitune-san wrote: ↑Mon May 30, 2022 1:42 pm
Synopsys Design Constraints (.sdc) files are created by the designer. It is not generated.
Even if SDC was not the cause of this problem, this file should be created.
Also needed for timing analysis.

kitune-san wrote: ↑Mon May 30, 2022 1:55 pm By the way, is the CPU clock at the time of RAM check 4.77MHz?

kitune-san wrote: ↑Tue May 31, 2022 12:17 pm I will fix the SDRAM.sv because the self refresh operation is not working.
CKE is not LOW during the refresh command.

kitune-san wrote: ↑Tue May 31, 2022 1:19 pm Could you tell me what SDRAM chip you are using?