MiSTer FPGA Forum

MicroCoreLabs wrote: ↑Sat Jun 11, 2022 6:26 am
I suggest looking at the SuperSoft manual for their explanation why Interrupt Level 0 fails. This test appears to cover the 8253, 8259, and the 8288.

kitune-san wrote: ↑Sat Jun 11, 2022 9:29 am In mode 0, if the count register is rewritten during counting, it stops.
Then, a second rewrite starts the count.
Apparently I have not incorporated this specification....

However, I do not know if this is the cause of this issue.

kitune-san wrote: ↑Sat Jun 11, 2022 11:47 am It is unlikely, but would you like to try timing constraints?
The clocks clk_14_318, clk_4_77, and peripheral_clock are not output from the PLL, so create_generated_clock is required.

For example: (As a reminder, this is not perfect.)
https://github.com/kitune-san/PCXT_MiST ... 2402da06ef

Note that the processing time of Fitter is very long.

kitune-san wrote: ↑Sat Jun 11, 2022 3:55 pm Sorry, DMA needed FF between timer output and DRQ.
Please wait a moment.

always_ff @(negedge clock) begin
	prev_timer_count_1 <= timer_counter_out[1];
end

always_ff @(negedge clock, posedge reset) begin
	if (reset)
		DRQ0 <= 1'b0;
	else if (~dma_acknowledge_n[0])
		DRQ0 <= 1'b0;
	else if (~prev_timer_count_1 & timer_counter_out[1])
		DRQ0 <= 1'b1;
	else
		DRQ0 <= DRQ0;
end

BUS_ARBITER u_BUS_ARBITER (
	....
	.dma_request                        ({dma_request[3:1]}, DRQ0},
	....
);

kitune-san wrote: ↑Sat Jun 11, 2022 4:11 pm

kitune-san wrote: ↑Sat Jun 11, 2022 3:55 pm Sorry, DMA needed FF between timer output and DRQ.
Please wait a moment.

in Chipset.sv

Code: Select all

always_ff @(negedge clock) begin
	prev_timer_count_1 <= timer_counter_out[1];
end

always_ff @(negedge clock, posedge reset) begin
	if (reset)
		DRQ0 <= 1'b0;
	else if (~dma_acknowledge_n[0])
		DRQ0 <= 1'b0;
	else if (~prev_timer_count_1 & timer_counter_out[1])
		DRQ0 <= 1'b1;
	else
		DRQ0 <= DRQ0;
end

BUS_ARBITER u_BUS_ARBITER (
	....
	.dma_request                        ({dma_request[3:1]}, DRQ0},
	....
);

kitune-san wrote: ↑Sun Jun 12, 2022 3:47 am MiSTer has been delivered to me.
At first, SuperSoftROM was booted and I was connected to the Signal Tap.
I will report back if I find out anything.

kitune-san wrote: ↑Sun Jun 12, 2022 5:15 am Passed!

kitune-san wrote: ↑Sun Jun 12, 2022 5:15 am Passed!

DSC_0131.JPG

wark91 wrote: ↑Sun Jun 12, 2022 9:22 am Do you plan to add more video output on this core ?
It is great to follow the development of this core on this thread !! Thanks

• MDA and CGA/Tandy now work at the same time. It is possible to switch from one to the other from the OSD menu, as well as their monochrome simulation independently.
• Fixed problem with INT0 test failing
• Fixed a bug that caused the timer counter to be cleared on latch.
• PCXT DIP switches and access to MDA memory
• Add port_b[6] to lock PS/2 CLK.
• PS/2 CLK to drop LOW after receiving the key code.

remax wrote: ↑Sun Jun 12, 2022 8:03 pm Do you plan to add HDD support back soon ?

Cause i don't have the serial cable (and a bit afraid by the voltage level things) and i die to try all of this...

breiztiger wrote: ↑Sun Jun 12, 2022 8:09 pm Floppy is perhaps more simple to implement

There is a lot of booter floppy disk to try

Bas wrote: ↑Sun Jun 12, 2022 8:26 pm Love to see this thing grow as openly as you are building it. Absolutely +1 on the Tandy. For nostalgia I'd drool over a working Hercules output as well but you do what you deem best. Thank you for the massive effort!

spark2k06 wrote: ↑Mon Jun 13, 2022 4:57 am Beta 0.8

https://github.com/spark2k06/PCXT_MiSTe ... d211158808

• MDA and CGA/Tandy now work at the same time. It is possible to switch from one to the other from the OSD menu, as well as their monochrome simulation independently.
• Fixed problem with INT0 test failing
• Fixed a bug that caused the timer counter to be cleared on latch.
• PCXT DIP switches and access to MDA memory
• Add port_b[6] to lock PS/2 CLK.
• PS/2 CLK to drop LOW after receiving the key code.

remax wrote: ↑Sun Jun 12, 2022 8:03 pm Do you plan to add HDD support back soon ?

Cause i don't have the serial cable (and a bit afraid by the voltage level things) and i die to try all of this...

I would like to, but it is not an easy task, and at the moment it is out of my reach. I've mentioned it to @JasonA to see if he can take a look at it, it would certainly make the core more usable for all users.

breiztiger wrote: ↑Sun Jun 12, 2022 8:09 pm Floppy is perhaps more simple to implement

There is a lot of booter floppy disk to try

It is simpler in principle than IDE, and I actually made a first attempt, but I got stuck with the 16-bit handling in the HPS part of MiSTer:

https://github.com/spark2k06/PCXT_MiSTer/tree/fdd-test

Bas wrote: ↑Sun Jun 12, 2022 8:26 pm Love to see this thing grow as openly as you are building it. Absolutely +1 on the Tandy. For nostalgia I'd drool over a working Hercules output as well but you do what you deem best. Thank you for the massive effort!

Yes, Hercules is another interesting option to evaluate in the future

jordi wrote: ↑Mon Jun 13, 2022 10:21 am I'm not sure if @sorgelic could take a look on this floppy integration. I guess it would be simple for the author

spark2k06 wrote: ↑Sun Jun 12, 2022 5:28 am now for the keyboard