MiSTer FPGA Forum

kitune-san wrote: ↑Mon Jun 13, 2022 1:43 pm I added keybord reset logic.
With this change, the keyboard controller test would pass.

I have sent you a pull request.
Please try it.

kitune-san wrote: ↑Mon Jun 13, 2022 2:16 pm

kitune-san wrote: ↑Mon Jun 13, 2022 1:43 pm I added keybord reset logic.
With this change, the keyboard controller test would pass.

I have sent you a pull request.
Please try it.

Sorry. 8088 BIOS does not seem to accept keyboard...
Please give me a little more time.

The next big challenge is to get the SDRAM working, so that the 640Kb of main memory is available for testing larger games

MicroCoreLabs wrote: ↑Mon Jun 13, 2022 5:45 pm You will get some nice acceleration if you provide the option to bypass the cycle-accurate BIU and access block-ram located BIOS ROMs and SDRAM at full-speed.

MicroCoreLabs wrote: ↑Mon Jun 13, 2022 7:07 pm Does your SDRAM controller have exclusive access to the physical SDRAM or does it share it with the SOC-CPU? If it is sharing, then when there are conflicts then you may need to assert wait-states back to the BIU. It would be better if the SDRAM access was exclusive to the MCL86, otherwise it may be difficult to be consistently cycle accurate if there is a CPU which can delay the BIU's accesses and cause wait states.

On the other hand, if the SDRAM is fast enough, it may be transparent to the 4.77Mhz BIU!

spark2k06 wrote: ↑Thu Jun 09, 2022 4:40 am
Finally, I attach the latest version of the XTIDE Universal BIOS and HD detection via the serial port by default, which can be loaded into memory from the OSD menu, as it will be loaded from address F0000h. The same you can do with JukoST, in this case you would have to prepare with a hex editor a 64Kb ROM with the XTIDE Universal BIOS at the beginning and JukoST at the end (from FE000h) and the same, you can load it in memory from the OSD menu.

kitune-san wrote: ↑Tue Jun 14, 2022 2:03 pm
..Or merge ROM files 8 times.
$ cat 8k_bios > boot.rom
$ cat 8k_bios >> boot.rom
$ cat 8k_bios >> boot.rom
$ cat 8k_bios >> boot.rom
$ cat 8k_bios >> boot.rom
$ cat 8k_bios >> boot.rom
$ cat 8k_bios >> boot.rom
$ cat 8k_bios >> boot.rom

copy /y /b 8k_bios+8k_bios+8k_bios+8k_bios+8k_bios+8k_bios+8k_bios+8k_bios boot.rom

spark2k06 wrote: ↑Tue Jun 14, 2022 2:25 pm

kitune-san wrote: ↑Tue Jun 14, 2022 2:03 pm
..Or merge ROM files 8 times.
$ cat 8k_bios > boot.rom
$ cat 8k_bios >> boot.rom
$ cat 8k_bios >> boot.rom
$ cat 8k_bios >> boot.rom
$ cat 8k_bios >> boot.rom
$ cat 8k_bios >> boot.rom
$ cat 8k_bios >> boot.rom
$ cat 8k_bios >> boot.rom

For Windows CMD:

Code: Select all

copy /y /b 8k_bios+8k_bios+8k_bios+8k_bios+8k_bios+8k_bios+8k_bios+8k_bios boot.rom

cat 8k_bios 8k_bios 8k_bios 8k_bios 8k_bios 8k_bios 8k_bios 8k_bios > boot.rom

cat 8k_bios$notexistvar{1..8} > boot.rom

kitune-san wrote: ↑Mon Jun 13, 2022 2:16 pm

kitune-san wrote: ↑Mon Jun 13, 2022 1:43 pm I added keybord reset logic.
With this change, the keyboard controller test would pass.

I have sent you a pull request.
Please try it.

Sorry. 8088 BIOS does not seem to accept keyboard...
Please give me a little more time.

kitune-san wrote: ↑Tue Jun 14, 2022 3:32 pm As a countermeasure, I am considering the following
- No forced LOW of clock by IRQ
- If the next data is received before the interrupt is released, temporarily set the IRQ signal LOW. (At this time, the scan code is 0xFF.)

EDIT:
I will try to fix 8259 module.

spark2k06 wrote: ↑Wed Jun 15, 2022 4:01 pm
I have tested the pull request you created:

https://github.com/spark2k06/PCXT_MiSTer/pull/8

Overall kernel performance is similar, IBM 5160 BIOS error 101 still occurs... but the downside is that the interrupt level 0 error in the SuperSoft test ROM has returned with this patch.

• 640Kb main memory with SRAM, until SDRAM is available... but perfect for porting to other FPGA

MicroCoreLabs wrote: ↑Fri Jun 17, 2022 5:35 pm With 640KB the 8088 MPH Demo should be able to run to completion. The music at the end uses the prefetch queue extensively, so it's a good test of the BIU.

kitune-san wrote: ↑Sat Jun 18, 2022 2:11 am @spark2k06
The problem with SDRAM not working is caused by the lack of timing constraints.
In my environment, it works fine by adding the following to PCXT.sdc.

Code: Select all

# core specific constraints
set_input_delay -clock { FPGA_CLK2_50 } -max 6 [get_ports { SDRAM_DQ[*] }]
set_input_delay -clock { FPGA_CLK2_50 } -min 3 [get_ports { SDRAM_DQ[*] }]
set_output_delay -clock { FPGA_CLK2_50 } -max 2 [get_ports { SDRAM_DQ[*] SDRAM_DQM* SDRAM_A[*] SDRAM_n*  SDRAM_BA SDRAM_CLK }]
set_output_delay -clock { FPGA_CLK2_50 } -min 0 [get_ports { SDRAM_DQ[*] SDRAM_DQM* SDRAM_A[*] SDRAM_n*  SDRAM_BA SDRAM_CLK }]

kitune-san wrote: ↑Sat Jun 18, 2022 3:34 am In the latest commit, the PCXT.sdc file appears to have been removed from the project.
I added the PCXT.sdc file to the project again and confirmed that SDRAM works.

2022-06-18 123540.png

dmckean wrote: ↑Sat Jun 18, 2022 3:38 am Now we just need either floppy or IDE support so those of us without COM adapters can play along at home.

MicroCoreLabs wrote: ↑Fri Jun 17, 2022 5:35 pm With 640KB the 8088 MPH Demo should be able to run to completion. The music at the end uses the prefetch queue extensively, so it's a good test of the BIU.