MiSTer FPGA Forum

Another update from Sega Saturn core update from Sergey, fixes in VDP1 and VDP2.

If can please support his efforts by joining his Patreon here: https://www.patreon.com/srg320/posts

I don't think I have anticipated anything game related as much as the possibility of this core being realised.

Is this the first we've seen of a commercial game running?

FoxbatStargazer wrote: ↑Mon Jul 26, 2021 2:44 pm Is this the first we've seen of a commercial game running?

YES! Amazing! Still a long way to go, but WOOOOA!

I think technically Earthworm Jim 2 was shown running before at the end of this video:

https://www.youtube.com/watch?v=FPrGh3L15Ag

Another update : earthworm jim 2 gameplay

Was wondering what license you will be releasing this under...? (Wondering because cps3 apparently has same CPU and if you would allow portions of your work to be imported to other cores)

There's also video of the BUG demo playing, including some sound.

so so so so so good! Just joined his Patreon!

this has had so much recent progress in such a short space of time.

i’m sure development has been going on for a long long time, but given the recent steps with actual running commercial software, surely it’s getting close now.

Saturn FPGA. Rayman (USA) demo play with music and sound effect (careful though it's not perfect, so watch your ears).
https://www.youtube.com/watch?v=FFxgvZ_H1vU

Saturn FPGA. Daytona USA.
https://www.youtube.com/watch?v=rWU0bri9CW4

Too much joy currently, between this and Robert's work. This is just too much happiness for us.

throAU wrote: ↑Mon Jul 19, 2021 3:29 pm

softtest9 wrote: ↑Tue May 11, 2021 4:54 pm I don't think the Saturn has that much RAM.

Would likely be more about bandwidth than capacity

Not just bandwidth, but the ability to have consistent access timings with the various concurrent things that are happening. There are 6 physically independent RAMs if I haven't somehow double-counted: CPU async RAM, CPU+SCU SDRAM, VDP1 RAM, VDP2 RAM, framebuffer RAM, sound RAM. A bunch of later games also have cartridge ROM/RAM, but I'll bet that's fine being in DDR3 (I'm not aware of anything that actually runs directly from cartridge space).

ExCyber wrote: ↑Sun Sep 12, 2021 6:45 pm I'm not aware of anything that actually runs directly from cartridge space).

KOF and Ultraman?

Given rom is generally slower than ram it should be fine with the slower shared ddr3 - layman’s guess.

I just remember a thing back in the day with PCs was to shadow the bios into ram to speed it up for DOS doing bios calls into it.

Slipard wrote: ↑Mon Sep 13, 2021 5:41 am

ExCyber wrote: ↑Sun Sep 12, 2021 6:45 pm I'm not aware of anything that actually runs directly from cartridge space).

KOF and Ultraman?

I haven't specifically looked at games, but Sega told developers to never store code in cartridges, and graphics/sound assets would need to be copied to an internal RAM before use. Action Replay obviously runs code stored on a cartridge, but I believe it also copies itself to RAM before actually running.

Daytona USA outta nowhere! Daytona USA outta nowhere! There I was enjoying my day and then I stumble upon this. I believe it's by the same wonderful developer bringing us this core.

Captain FPGA wrote: ↑Tue Sep 14, 2021 3:03 am I believe it's by the same wonderful developer bringing us this core.

Yes it was linked in the last Patreon post.

Chris23235 wrote: ↑Tue Sep 14, 2021 5:50 am

Captain FPGA wrote: ↑Tue Sep 14, 2021 3:03 am I believe it's by the same wonderful developer bringing us this core.

Yes it was linked in the last Patreon post.

I know decided to post it here too.

When (if) this core is released will it accept CHD files like most of the other disc based consoles?

Woah, did this guy build the CPU and the graphics chips both from scratch? Saturn has a pretty oddball CPU.

douglasamcintosh wrote: ↑Tue Sep 14, 2021 4:48 pm When (if) this core is released will it accept CHD files like most of the other disc based consoles?

CHD and BIN/CUE support is implemented entirely within Main_MiSTer, so it's basically independent of the core. There's a bit of 'glue' in Main that's specific to each core (since they all have some quirks) but the majority of the heavy lifting is non-core specific.

Assuming this core is implemented like other CD based cores, if the initial release doesn't include CHD support I'll add it like I did for the current CD-based cores.

cathrynmataga wrote: ↑Tue Sep 14, 2021 5:00 pm Woah, did this guy build the CPU and the graphics chips both from scratch? Saturn has a pretty oddball CPU.

All of the CPUs in the Saturn are normal CPUs: it uses a pair of Hitachi SH-2s, an SH-1, and a 68000. Maybe you're thinking about the VDPs? Most machines of this and previous generations used custom chips for the graphics, but the CPUs are all normal parts that are used in many other devices.

The SH family isn't all that common though - nothing like the M68k. So I could well imagine that srg wrote his own SH-1 and SH-2 implementations. Fortunately they have pretty small instruction sets, so as far as processors go, those should be pretty easy to implement. At least that's my experience from writing software emulators, though I don't know how well that carries over to FPGA development.

mic_ wrote: ↑Wed Sep 15, 2021 8:10 am The SH family isn't all that common though - nothing like the M68k. So I could well imagine that srg wrote his own SH-1 and SH-2 implementations. Fortunately they have pretty small instruction sets, so as far as processors go, those should be pretty easy to implement. At least that's my experience from writing software emulators, though I don't know how well that carries over to FPGA development.

The SH-2 has an open source implementation now (J-Core) as Hitachi let the patents expire.

https://j-core.org/

The 68000 has already been done

The VDP1 and VDP2 would definitely need re-implementing from scratch

throAU wrote: ↑Wed Sep 15, 2021 9:38 am

mic_ wrote: ↑Wed Sep 15, 2021 8:10 am The SH family isn't all that common though - nothing like the M68k. So I could well imagine that srg wrote his own SH-1 and SH-2 implementations. Fortunately they have pretty small instruction sets, so as far as processors go, those should be pretty easy to implement. At least that's my experience from writing software emulators, though I don't know how well that carries over to FPGA development.

The SH-2 has an open source implementation now (J-Core) as Hitachi let the patents expire.

https://j-core.org/

The 68000 has already been done

The VDP1 and VDP2 would definitely need re-implementing from scratch

SH1/SH2 is not only a SuperH processor core, but also contains some peripheral modules. J-Core does not match me because it has separate buses for instructions and data as well as the caches, also does not contain most of the peripheral modules.

For 68000 I use fx68k core of course.

Thanks for the info!

The Cyclone V in the De10-Nano has 41,910 ALMS in 110k LEs, so according to srg's chart the SH1/SH2 chips seem to take up about one fourth of the FPGA capacity.

Also worth pointing out that the 32X and CPS-3 also use SH-2 processors so this hard work is paving the way for those cores in the future.

Mr. Encyclopedia wrote: ↑Wed Sep 15, 2021 6:57 pm Also worth pointing out that the 32X and CPS-3 also use SH-2 processors so this hard work is paving the way for those cores in the future.

Did not know that!

It would be great to see CPS3 reproduced in MiSTer

I hope we ll see SF3.3 CPS3 for the MiSTer.