MiSTer FPGA Forum

spark2k06 wrote: ↑Sat Jun 18, 2022 4:06 am If you have a working version, can you update this branch with the changes, or... can you provide the synthesised .rbf file here for me to test?

thorr wrote: ↑Sat Jun 18, 2022 4:18 am

dmckean wrote: ↑Sat Jun 18, 2022 3:38 am Now we just need either floppy or IDE support so those of us without COM adapters can play along at home.

I am not sure if IDE would even work with this. Back then, the drives were RLL or MFM from what I recall.

kitune-san wrote: ↑Sat Jun 18, 2022 4:25 am

spark2k06 wrote: ↑Sat Jun 18, 2022 4:06 am If you have a working version, can you update this branch with the changes, or... can you provide the synthesised .rbf file here for me to test?

Please give it a try.

kitune-san wrote: ↑Sat Jun 18, 2022 4:41 am

kitune-san wrote: ↑Sat Jun 18, 2022 4:25 am

spark2k06 wrote: ↑Sat Jun 18, 2022 4:06 am If you have a working version, can you update this branch with the changes, or... can you provide the synthesised .rbf file here for me to test?

Please give it a try.

Apparently, sometimes they succeed and sometimes they fail.
More timing adjustment is needed.

spark2k06 wrote: ↑Sat Jun 18, 2022 5:02 am Apparently, the rbf you sent is working fine for me . Can you update your branch add-sram with this change?

Malor wrote: ↑Sat Jun 18, 2022 5:27 am FWIW, I don't think it's any problem hooking an IDE interface up to an XT. The real things didn't have IDE, but AFAIK it will retrofit perfectly. Trying to rebuild MFM and RLL drives would probably be a lot of work for no particular benefit.

The Monotech NuXT, for instance, has an IDE controller built into the motherboard:

https://monotech.fwscart.com/NuXT_v20_M ... 77986.aspx

edit: I mean, with real MFM drives, you had to silver them yourself (low-level format) by running DEBUG and jumping to a specific address in the ROM BIOS. The command might have been g=c800:6, but I'm probably not quite right there. That would pop you into a BIOS interface where you would manually choose the drive interleave and lay down a low-level format, carefully entering the bad sectors that were on a sticker on top of the drive. And woe betide you if you chose an interleave that was wrong.... too loose and the drive would be slower than it should be, but too tight and the drive would take a gigantic performance hit. Only then would you do a high level partition and FAT format.

I mean, that whole setup sucked terribly. MFM and RLL were awful. Dealing with all that nonsense is just silly when you're dealing with virtual drives that don't have interleave and don't have bad sectors. IDE will be so much better.

It turns out that at some point it stopped working as "well" as it used to. It used to go further but now, even with 640Kb of RAM, it stays in this part of the demo, in a loop:

MicroCoreLabs wrote: ↑Sat Jun 18, 2022 5:35 am

It turns out that at some point it stopped working as "well" as it used to. It used to go further but now, even with 640Kb of RAM, it stays in this part of the demo, in a loop:

The demo uses multiple HALT opcodes in a row in combination with an interrupt to synchronize timing. If your interrupts are not correct it could explain why you are getting stuck here.

I suggest simulating your 8253 and 8259 in a small test bench to thoroughly debug their functionality. The design also should be fully constrained, otherwise you could get inconsistent results between synthesis passes, over temperature, and between devices.

kitune-san wrote: ↑Sat Jun 18, 2022 4:41 am
Apparently, sometimes they succeed and sometimes they fail.
I noticed this by turning the power on and off repeatedly.

More timing adjustment is needed.

spark2k06 wrote: ↑Sat Jun 18, 2022 8:07 am However, if it happens to you, it will happen.... any improvement in this respect will be welcome, thanks!!!

spark2k06 wrote: ↑Sat Jun 04, 2022 5:59 am I have built myself a DB9 -> USB cable with an adapter:

db9-usb.jpg

From the next pinout of the DB9 connector:

Code: Select all

DB9 MiSTer
 
1 - DSR
2 - N/C
3 - TX
4 - RTS
5 - VCC (5V)
6 - CTS
7 - RX
8 - GND
9 - DCD
Shield - DTR

logically, by crossing the signals: TX <-> RX, DSR <-> DTR and RTS <-> CTS. I have not connected VCC because it is not necessary in this case. The USB is already powered directly from the PC.

It looks like there is communication, but I get checksum error and the HD image is not detected:

serdrive.png

Last changes:

https://github.com/spark2k06/PCXT_MiSTe ... 009305dfa0

There always seems to be a problem... I'll get back to the floppy or IDE booting line of work.

flynnsbit wrote: ↑Sun Jun 19, 2022 3:58 am
I'm thinking about forging ahead and trying the serial loading of images with xtide. tomorrow. I have a couple of questions.

1. So on this adapter you connected the usb to a modern PC and set up serdrive to host it over the com associated in windows to the adapter you connected. At what speed, error control etc? 9600,8,1?

2. That adapter on the serial side is plugging directly into the USer IO port on a Mister IO board into the IO Port (USB style) or into Antonio's DB9 implementation of the Serial interface? If USB I/O are you using a level converter or just something straight like this: https://misterfpga.co.uk/product/mister ... -adapters/ if you pick the Sega adapter??

3. verify the speed you are running serial at to get them both to talk to each other.

I've started on an image with CGA only games that run either 4 or 7mhz with MyMenu. I already had this for my real PCJr so I am just converting it to this core. Once we get VHDs/IDEs I can do updates from Github for the contents of the "Packs"

This core is my holy grail and I am so enjoying ya'll working openly with it on the forum. Thank you for doing that.

	//
	// Pin | USB Name |   |Signal
	// ----+----------+---+-------------
	// 0   | D+       | I |RX
	// 1   | D-       | O |TX
	// 2   | TX-      | O |RTS
	// 3   | GND_d    | I |CTS
	// 4   | RX+      | O |DTR
	// 5   | RX-      | I |DSR
	// 6   | TX+      | I |DCD
	//

serdrive.exe -c <port> -d 115.2KB <image>

• Increased RAM mapping in SDRAM: 0x00000-0xAFFFF and 0xC0000-0xEFFFF

spark2k06 wrote: ↑Mon Jun 20, 2022 5:48 am
With this new feature, I tried the Use!UMB.sys application, and then used DOSMAX to maximise the conventional memory available, but there must be some bug in the core that makes it hang:

wark91 wrote: ↑Mon Jun 20, 2022 11:24 am Thank you !
Is DOSMAX really usefull for PCXT softwares (programs, games, etc ...) ?
Have you tried DOS/V (a japanese version of DOS) on the current core ?

kitune-san wrote: ↑Mon Jun 20, 2022 1:05 pm

spark2k06 wrote: ↑Mon Jun 20, 2022 5:48 am
With this new feature, I tried the Use!UMB.sys application, and then used DOSMAX to maximise the conventional memory available, but there must be some bug in the core that makes it hang:

I do not know about access to RAM in the UMB area.
Does this automatically recognize RAM in the UMB area?
Or is it something that needs to be configured beforehand?

...Actually, I am not familiar with PC/AT/XT and 8/16-bit old CPUs.
I was born in 1994 and the first PC I used had windows 2000 installed.
The 640k barrier had already broken.
So I need a lot of information to know what is going on.

• Tapper (Error Disk)
• Bubble Bobble
• Solomon's Key (No movement of the character, cursors)
• Popcorn (no movement of the shovel, cursors)
• Centipede (Ship goes to the left by itself and shoots continuously)
• Game Over
• Phantis
• Robocop
• Prohibition (can't get past the menu, problem with the keyboard)
• Boulder (problem with the keyboard)

breiztiger wrote: ↑Mon Jun 20, 2022 3:12 pm Hi

Before ems, can you look at floppy ?

We can help you more easily than actualy with serial

Thanks for your hard work on that neat core

kitune-san wrote: ↑Tue Jun 21, 2022 2:58 pm The 101 error in the original XT BIOS was caused by not using DMA for memory refresh.
It's experimental. If the following change is made to return 0x01 on the status read, the 101 error will no longer occur.
However, it then stops with error 601.

In the future, I would like to perform SDRAM refresh by DMA events.

In KF8237.sv, line 241
2022-06-21 235000.png

kitune-san wrote: ↑Tue Jun 21, 2022 2:58 pm The 101 error in the original XT BIOS was caused by not using DMA for memory refresh.
It's experimental. If the following change is made to return 0x01 on the status read, the 101 error will no longer occur.
However, it then stops with error 601.

In the future, I would like to perform SDRAM refresh by DMA events.

In KF8237.sv, line 241
2022-06-21 235000.png

spark2k06 wrote: ↑Tue Jun 21, 2022 4:36 pm As for floppy, I have been tipped off about the existence of a module that could be a candidate to be used, I think it only lacks the DMA signals, which I don't know to what extent they are essential... it's from the MiSTer Acorn Archimedes core:

https://github.com/MiSTer-devel/Archie_ ... er/rtl/fdc

We will have to take a look at it and see what can be done.