Lets actually try Hybrid Emulation

[Fularu]

Interesting to see that the new Rev1.8 Miniming card from 2022 proposes also a kind of hybrid with the Pistorm (running official core and Emu68)
I really like their statement : "PiStorm compatibility – Using optimized Emu68 over 800MIPS of CPU performance! About 3-4X speed of Vampire. "
https://www.minimig.ca/index.php/produc ... 1-8-green/

It's kind of unfortunate that this version of Minimig doesn'T support AGA.

Aga with PiStorm would be quite an amazing thing. Much more so imho than with Buffee. I know there's an upcoming TF1200 with a 68000 dip socket so that you can plug a buffee or PiStorm but that would be one more card for me (along with my TF1260 and 1230 MK IV)

Strange it does not support AGA? I thought AGA support for Minimig came from the Minimig? Or maybe it was developed on the MiST first? I just know it was ported to the MiSTer rather than developed on the MiSTer. Just like the RTG feature was not a feature the MiSTer got first.

The official Minimig boards only support up to ECS

[Malor]

I think they added AGA on Mister because there was more room on the FPGA.

[kolla]

AGA was first implemented on the MiST, before the MiSTer came along. And yes, larger FPGA.

[Malor]

I didn't realize that Minimig and MiST were not the same thing. Oops!

[Caldor]

AGA was first implemented on the MiST, before the MiSTer came along. And yes, larger FPGA.

Was it MiST first, or was it TC64 first? Pretty sure some features were TC64 first. I am somewhat certain 020 support was done on TC64 first.

[Chris23235]

AGA was first implemented on the MiST, before the MiSTer came along. And yes, larger FPGA.

Was it MiST first, or was it TC64 first? Pretty sure some features were TC64 first. I am somewhat certain 020 support was done on TC64 first.

The current Minimig AGA core is based on Rok Krajnc's original Minimig core, from what I see the AGA support was introduced to this core by him for the MiST in 2014:

http://somuch.guru/minimig/minimig-mist/

The current core called Minimig AGA was developed on the basis of the original Minimig core by Ronbinsonb5 with both TC64 and MiST in mind:

https://github.com/minimig-dev/MinimigAGA-MiST-TC64

[robinsonb5]

Was it MiST first, or was it TC64 first? Pretty sure some features were TC64 first. I am somewhat certain 020 support was done on TC64 first.

You're right that '020 support came to TC64 first (it might have come to C-One even before that, though - I'm not sure!)

The history of the Minimig core is surprisingly tangled, and I took the time to document some of it a year or so back: http://retroramblings.net/downloads/Min ... lyTree.pdf

Tobias Gubener (The TG of TG68) had combined the Minimig chipset code with his own CPU implementation, and had ported the resulting core to C-One, DE1 and Turbo Chameleon 64.
I came on the scene when I bought a TC64, and made some improvements to that version of the core, including a redesign of the menu. (That vertical stripe with the core name reversed out of it? Yup, that came to TC64 first.)

Rok adopted the DE1 version of the core, and pulled in the changes from my TC64 version, and it was Rok's DE1 version which was the basis for Minimig on MiST. That's the platform on which Rok subsequently developed the AGA core. (The Replay team actually got there first, with their own independently-developed AGA core, but it was never opened so has so far only been seen on Replay hardware.)

The MiST AGA core was, of course, the basis for the MiSTer AGA core.

When I returned to FPGA dev a few years ago I ported the MiST AGA core (now maintained by Slingshot) back to TC64, then added the RTG system, using the newly-opened Replay RTG driver's source code as an example for my own driver. To avoid yet more fragmentation, Slingshot and I merged the MiST and TC64 cores in a single repo, which is the one Chris23235 linked to in the previous post.

The RTG system on Minimig MiSTer which Grabulosaure added is different, but works in a similar way to mine.

[Caldor]

Nice Thanks for the contributions to the FPGA cores Robinson

[Solskogen]

Is there anything in the MiST/TC64 Minimig core that's not in MiSTER Minimig core (or vice versa)?

[ToothbrushThreepwood]

Is there anything in the MiST/TC64 Minimig core that's not in MiSTER Minimig core (or vice versa)?

MiST/TC64 supports dual mouse like the original amiga, so it support multiplayer in games such as Lemmings and The Settlers, unlike MiSTer.

Edit: I believe brobinson himself did the implementation on the TC64.

[robinsonb5]

Edit: I believe brobinson himself did the implementation on the TC64.

It's hard to keep track of who did what, but I think the dual mouse support was Slingshot's work. TC64 doesn't have USB ports, so dual mouse only works with the Docking Station and a real Amiga mouse in the DB9 port, I think.

TC64/MiST also has an extra audio path, 16-bit 44.1KHz, with a WAV player - but no AHI driver yet. (On TC64 - but not MiST - I use that audio path for imitation floppy and hard drive sounds.)

[kolla]

Meanwhile, in Canada, orginal Minimig had a bit of a revival and evolved into a 1.3 and even a 1.8 variant with DIP68 socket that can take real 68000 chips, as well as fun stuff like PiStorm and Buffee (which is what it was made for). I don't know if they have done anything to the FPGA cores though...

https://www.minimig.ca

Personally, I've been using my old minimig v1.1 quite a lot lately, just wish there was a way to attach 8MB of fastram to that 68SEC000...
(in my mind, a thin pcb holding the ram, with a square opening for the 68sec000, and solder points along the inner edge of the opening)

[jca]

I think 1.1 is the only interesting one: a nice little package at an OK price, ideal for traveling but as you said a little short on memory. The other versions are way too expensive, for that price you can get a DE10 nano + SDRAM + basic unpowered OTG hub.
These people are also insane: did you see the huge price variation depending on the PCB color?
Their web site also sucks: absolutely no technical information, no manual to download, not even a download page for anything. You also do not know what you are buying: for example with 1.1 which comes with a PIC it does not say which PIC you get. There are 2 PIC and also an ARM, clicking on each of these options it seems that it comes with the new PIC, each of these pages gives info on the ARM one so it is difficult to know what are the differences.

[bbond007]

Personally, I've been using my old minimig v1.1 quite a lot lately, just wish there was a way to attach 8MB of fastram to that 68SEC000...
(in my mind, a thin pcb holding the ram, with a square opening for the 68sec000, and solder points along the inner edge of the opening)

My 1.1 has stacked RAM chips for 4MB. I bought it that way, but I know 4mb is possible. That minimig.ca only offers up to 4mb so maybe there is just not enough free IO for the chip selects.

[H6rdc0re]

Let me start this post with me saying I can't code and know nothing about HDL.

I've been reading ARMv7 is backwards compatible with ARMv4, ARMv5te and ARMv6 instructions. With a Nintendo DS core currently being touted impossible on Mister. Would it be possible to run the ARM946E-S (ARMv5TE) CPU code on one of the ARM A-9 Cortex CPU's instead? Leaving room on the FPGA for the 2D part of the GPU and maybe even the 3D part. Perhaps there are other reasons why a Nintendo DS core is not possible but I thought it's an interesting example where hybrid emulation could work.

I couldn't find anything about backwards compatibility with ARM60 (ARMv3) but perhaps 3DO CPU code could run natively on an ARM A-9 CPU core. Perhaps a way to a 3DO core??

[kolla]

Personally, I've been using my old minimig v1.1 quite a lot lately, just wish there was a way to attach 8MB of fastram to that 68SEC000...
(in my mind, a thin pcb holding the ram, with a square opening for the 68sec000, and solder points along the inner edge of the opening)

My 1.1 has stacked RAM chips for 4MB. I bought it that way, but I know 4mb is possible. That minimig.ca only offers up to 4mb so maybe there is just not enough free IO for the chip selects.

Yes, 4MB, of which 512k is reserved for holding kickstart, up to 2 MB of chipram and 1.5 MB of "slow ram", public memory available through Agnus.

My wish is about fast ram, directly attached to the CPU, just like fast ram boards you can strap ontop of the 68000 chip on A600.

[Neocaron]

Let me start this post with me saying I can't code and know nothing about HDL.

I've been reading ARMv7 is backwards compatible with ARMv4, ARMv5te and ARMv6 instructions. With a Nintendo DS core currently being touted impossible on Mister. Would it be possible to run the ARM946E-S (ARMv5TE) CPU code on one of the ARM A-9 Cortex CPU's instead? Leaving room on the FPGA for the 2D part of the GPU and maybe even the 3D part. Perhaps there are other reasons why a Nintendo DS core is not possible but I thought it's an interesting example where hybrid emulation could work.

I couldn't find anything about backwards compatibility with ARM60 (ARMv3) but perhaps 3DO CPU code could run natively on an ARM A-9 CPU core. Perhaps a way to a 3DO core??

You should go ask FPGAzumpass on Twitter, since he is the one who worked on the DS core. I'm sure between that between the hybrid approach and the Kernel overclock from Coolbho3k, there is potentiel to make it work.
I know that Coolbho3k is exploring overclocking the DDR3 memory as well and I'm sure this would help for many many things regarding better latency.

[Caldor]

I was trying out the Hybrid core, and I cannot seem to get it to run anymore.

Maybe the Linux updates has stopped it from working? I ran the script to switch to the Hybrid MiSTer Main and then I ran the HybridMinimig core, but I could not get it to boot with the 68Arm CPU. It could just be that I have done something to the emulation files, but I do not remember having done anything to them, so I think it might be because of all the updates to the Linux subsystem. Just maybe a bit strange if it works as well as it does, and then just not when booting with the 68Arm CPU. Because it does boot with the 020 CPU when using the Hybrid core.

[Caldor]

Might not have to do with the MiSTer Main update. I tried updating the Hybrid MiSTer Main with the newest stuff, and I got the same error, and it does work with Mushashi just not with QEMU. But with Mushashi the 040 core runs as a 030 and I do think QEMU used to actually be able to boot, and it doesnt now. So now I am trying to also update the MinimigHybrid core, but it keeps failing. But then, merging the gits does not seem to be enough, I keep getting the QSF file and when I did get it to start to compile it would get an error.

While Mushashi does boot, its not stable enough to run anything. At least The Settlers which I was trying to test, just keeps crashing when I try to boot it. It could play the intro but crashes before getting into the game. Does not even get to the part with the code and menu music.

[MicroCoreLabs]

Hi,

I thought I would share some of my results with this thread as another datapoint on hybrid emulation.

One of my recent projects is the MCL86+ which is an 8088 emulation running on an 800Mhz Teensy 4.1. There is enough CPU power to emulate the 8088 at near x386 speeds as well as the local bus interface.

Using this platform I am able to run a 6502, 6510, Z80, and 8088 as cycle accurate and substantially accelerated modes. Here is a link to my blog: https://microcorelabs.wordpress.com

The HPS CPU core in MiSTer has a similarly powered CPU (but is not superscalar I believe), so should be able to get similar results; and could even have the advantge of implementing the local bus in the FPGA fabric rather than doing it in indeterministic software.


Thanks,
-Ted

[Neocaron]

Hi,

I thought I would share some of my results with this thread as another datapoint on hybrid emulation.

One of my recent projects is the MCL86+ which is an 8088 emulation running on an 800Mhz Teensy 4.1. There is enough CPU power to emulate the 8088 at near x386 speeds as well as the local bus interface.

Using this platform I am able to run a 6502, 6510, Z80, and 8088 as cycle accurate and substantially accelerated modes. Here is a link to my blog: https://microcorelabs.wordpress.com

The HPS CPU core in MiSTer has a similarly powered CPU (but is not superscalar I believe), so should be able to get similar results; and could even have the advantge of implementing the local bus in the FPGA fabric rather than doing it in indeterministic software.


Thanks,
-Ted

Glad to see someone bringing this thread back to life. You should look into the overclock kernel for the arm CPU on the Mister. I think at 1.2ghz you would get massive gain.
The temp changes are very light from the first tests (1C maximum). It would help massively for the minimig as well. Some people are on the fence about thi, but I think there is a lot of untapped potentiel here.

[MicroCoreLabs]

Some people are on the fence about thi, but I think there is a lot of untapped potentiel here.

Yeah, I believe the argument for keeping the CPU and peripherals in the FPGA fabric is because it is easier to port between FPGA vendors. SOC CPUs are less so...

But that said, these processors in the FPGA are only going to get more powerful giving more reason to emulate these sub 10Mhz CPUs using software. . There is probably already enough power to also emulate the motherboard peripherals as well.

[docbobo]

Okay - now that this thread is alive again: has anybody recently been able to run this? Tried yesterday with the archive from January (!) from a few pages back and was completely unsuccessful. Saw some errors regarding exec of setup, along the lines on unknown executable format (or so) and some warning loading the modules. Not sure if that's related since this is the first time I am trying...

[Bas]

The issue is probably in a mismatch between the package and the newer Linux kernel and supporting libs since then. A recompile of any executables is in order then.

[foft]

I updated my mister. The kernel build did change, but the version is the same. I guess just a recompile to change settings. So, the modules do not need recompiling.

If I put back the old patched MiSTer binary from here (https://github.com/scrameta/MiSTer_Hybrid_Support) then minimig hybrid still works.

Anyway I'll update and rebuild the core and patched MiSTer to get them up to date...

[foft]

Updated core and MiSter here in here:
https://github.com/scrameta/MiSTer_Hybrid_Support

They seem to work fine.

I checked musashi, no changes on github. There are updatee to qemu, I might give it a spin to see if it works but don't expect anything significant.

[foft]

I updated qemu, but it failed with an unaligned access exception. So I've not committed that build for now. This is the issue I had before with the last update until I found a single qemu patch to revert(https://github.com/qemu/qemu/commit/0ca ... 8ef78de5f4). I tried the equivalent change, with no improvement.

[Neocaron]

Updated core and MiSter here in here:
https://github.com/scrameta/MiSTer_Hybrid_Support

They seem to work fine.

I checked musashi, no changes on github. There are updatee to qemu, I might give it a spin to see if it works but don't expect anything significant.

Have you tried it with the 1.2ghz overclocked? If so what are you results in the benchmark? When I tried dosbox a while ago, the bench had some crazy numbers like 80% better performance for some reason. Even though it was only a 50% OC. So I'm wondering how it translate with the hybrid minimig.

[foft]

No, I'll have a try.

I was just trying it with the preemptive kernel patch (https://mirrors.edge.kernel.org/pub/lin ... s/rt/5.15/). It boots and works though didn't feel better in workbench, though I've not actually measured interrupt latency with it.

[foft]

So with the overclock patches on my rt kernel and sysinfo fake dhrystones:
400MHz: 4368, 4.6 Mips, 1.3 Mflops
800MHz: 35589, 37.1 Mips,9.6 Mflops
1000MHz: 50494, 52.7 Mips, 13.6 Mflops
1200MHz: 65776, 68.7 Mfips, 17.6 Mflops