MiSTer FPGA Forum

There is still something wrong with the graphics screen. 200 lines cannot be displayed normally. The 400 line is displayed normally on DE0-CV to some extent, but for some reason MiSTer crushes the height in half.

Hi Puu,
I have the same issue no OSD with the last RBF Zet98_20210109.
Thanks,

puu wrote: ↑Sat Jan 09, 2021 2:04 am I uploaded the latest Template core compiled with Advanced Setting (Synth and Fitter) of Compiler Settings.
https://fpga8801.up.seesaa.net/image/Zet98_20210109.rbf

Sorry, puu san ! Same behaviour and nothing new. I think you've got a problem with video timmings.

puu wrote: ↑Sat Jan 09, 2021 2:04 am I uploaded the latest Template core compiled with Advanced Setting (Synth and Fitter) of Compiler Settings.
https://fpga8801.up.seesaa.net/image/Zet98_20210109.rbf

Hello Mr Puu

Same issue with the last release of your Core and the last release of the main MiSTer.
With MiSTer_20201027, no issue

What exactly is Quartus giving an error message on the VIDEO clock?

puu wrote: ↑Sat Jan 09, 2021 2:04 am I uploaded the latest Template core compiled with Advanced Setting (Synth and Fitter) of Compiler Settings.
https://fpga8801.up.seesaa.net/image/Zet98_20210109.rbf

Hi puu,

As mentioned by other users above, same behaviour here.

At this moment I am not at my computer, but I remember that it had to do with a video clock.
Something like: CRTC98 : VID | VTIMING : TIM | clk3sft was determined to be a clock but was found without an associated clock assignment.

I have this line :
Warning (332060): Node: emu:emu|Zet98MiSTer:Zet98_top|CRTC98:VID|VTIMING:TIM|clk3sft[2] was determined to be a clock but was found without an associated clock assignment.
Info (13166): Register emu:emu|Zet98MiSTer:Zet98_top|CRTC98:VID|synccont2:sync|altshift_taps:HSYNCB_rtl_0|shift_taps_ibv:auto_generated|altsyncram_rcc1:altsyncram5|ram_block8a1 is being clocked by emu:emu|Zet98MiSTer:Zet98_top|CRTC98:VID|VTIMING:TIM|clk3sft[2]

Full compilation log:

puu wrote: ↑Fri Jan 08, 2021 2:40 pm I updated MiSTer to the latest version with update.sh earlier, and it became v210103, but it starts normally with the original binary.
Just in case, I uploaded a replacement of sys with the latest template core.

https://fpga8801.up.seesaa.net/rtl/rele ... MiSTer.rbf

Hello,

But why don't you have an issue with the latest version of Main MiSTer? It doesn't work for anyone !

The OSD lockup seems to be related to the parsing of CONF_STR. Commenting out the following line (in Zet98/MiSTer/Zet98.sv) fixed it for me. I don't understand why, because I don't see anything wrong with the syntax; I just found it by trial and error. The core still doesn't run consistently on my setup, but I think that's a different issue.

Bang ! Bingo !

ExCyber , you got the key. Thanks.

After several I / O errors, I realized that from the OSD (which already works) you can configure the options of the machine.
So once I checked it was working and with a DOS 6.2 disk for PC98, this is the result.
I'll take a look, there's a lot to test.

Thank you @puu for your hard work
Thank you @ExCyber,
Works also on my side with the latest Mister revision

I did some more experiments. The OSD hang happens when the combination of option name and current value is too long. The combination of "DIP2-6 Fixed drive" and "Disconnect" is 2 characters too long. So one possibility for why puu (or anyone else) might not see this problem is a saved setting of "DIP2-6 Fixed drive" to "Connect", which does not cause the problem.

Likewise, one workaround is to replace "Fixed drive" with "Hard disk", which is two characters shorter (but sadly loses 100% of the '80s PC jargon vibe). I've attached a .rbf with that change in case it's important to anyone to be able to flip that switch, although it sounded like HDD emulation isn't working yet (?).

I'm not sure what the actual failure is, but I guess it's probably something to do with overlapping memory regions in the menu code (various typical algorithms and library functions don't work correctly for overlapping regions).

@ExCyber,
Many thanks for sharing your findings.

Guys,
Would you please let me know if you have managed to run any .d88 games? All the ones I have tried so far boot up but have many graphical glitches/issues as if the screen was replicated 3/4 times.
Thanks!

Alkadian wrote: ↑Mon Jan 11, 2021 11:32 am Would you please let me know if you have managed to run any .d88 games?

I tried converting some .fdi games to .d88, I only get a DOS loading screen and then it goes black...

Maxriptide wrote: ↑Thu Jan 14, 2021 5:06 pm

Alkadian wrote: ↑Mon Jan 11, 2021 11:32 am Would you please let me know if you have managed to run any .d88 games?

I tried converting some .fdi games to .d88, I only get a DOS loading screen and then it goes black...

Thanks for your feedback. Hopefully this will get fixed soon.

Alkadian wrote: ↑Mon Jan 11, 2021 11:32 am @ExCyber,
Many thanks for sharing your findings.

Guys,
Would you please let me know if you have managed to run any .d88 games? All the ones I have tried so far boot up but have many graphical glitches/issues as if the screen was replicated 3/4 times.
Thanks!

I used HXCexplorer to convert the the .fdi to d88 but I got the same as your result, the game is unplayable due to many graphical glitches

Same here, all games I converted with VFIC showed only garbled graphics.

@ kathleen
@ Chris23235

Thanks for your feedback as well!

Thank you everyone for investigating the reason why it does not start.
I uploaded the corrections for that part and other corrections.

http://fpga8801.seesaa.net/archives/20210115-1.html

The standard state is the following settings.
DIP1-8 Extend
DIP1-3 Normal
DIP2-1 1
DIP2-2 Basic
DIP2-3 80
DIP2-4 25
DIP2-5 Keep
DIP2-6 Connect
DIP2-7 Control
DIP2-8 2.5MHz

puu wrote: ↑Fri Jan 15, 2021 11:20 am Thank you everyone for investigating the reason why it does not start.
I uploaded the corrections for that part and other corrections.

http://fpga8801.seesaa.net/archives/20210115-1.html

The standard state is the following settings.
DIP1-8 Extend
DIP1-3 Normal
DIP2-1 1
DIP2-2 Basic
DIP2-3 80
DIP2-4 25
DIP2-5 Keep
DIP2-6 Connect
DIP2-7 Control
DIP2-8 2.5MHz

Hello
Thank yo Mr Puu

Zet98_20210115

puu wrote: ↑Fri Jan 15, 2021 11:20 am Thank you everyone for investigating the reason why it does not start.
I uploaded the corrections for that part and other corrections.

http://fpga8801.seesaa.net/archives/20210115-1.html

The standard state is the following settings.
DIP1-8 Extend
DIP1-3 Normal
DIP2-1 1
DIP2-2 Basic
DIP2-3 80
DIP2-4 25
DIP2-5 Keep
DIP2-6 Connect
DIP2-7 Control
DIP2-8 2.5MHz

Hi Puu,

That's great, many thanks. I can't wait to test it!

tontonkaloun wrote: ↑Fri Jan 15, 2021 12:01 pm Zet98_20210115

That's very handy as usual. Many thanks for sharing tontonkaloun!

Hi,

Thank you puu for the updated core. It boots into DOS just fine, but I'm still getting the corrupted/duplicated screen issues Alkadian described. Here's what I'm seeing:

Even on Thexder, Hatris etc similar dual screen.

Thank you Mr Puu for the last release
I will test

Added support for 200 lines of graphics screen.

Interesting core, I hope the 8086 part can be used for other PC MS-DOS cores.

Thank you puu, its graphics glitch gone.