MiSTer FPGA Forum

All,

I am developing a core that uses USERIO.

Somehow, and I checked with a Logic Analyser, I cannot get the signals to appear on P7 pins 0,1,4,5,6,7 and 9.
I tried to understand what sys_top.v does. I understand that when I leave all slide switches in the OFF state the USERIO should appear.
In my case all driven signals stay 0. I connected a simple clock counter to the bits, driven by the system clock, and expected to see nice pulses.

If I put it in input by writing 1 to USER_OUT[x] then the signal stays high which is expected high impedance.

What am I missing? Do I have to enable something?

Regards,

Mario

These are open-drain ports; putting 1 in USER_OUT[x] places it in high-impedance mode, which is pulled high by a pullup resistor (for example, on the SNAC board).

So the only two states are '0' and 'high impedance', so this is how you would send the values '0' and '1'.
In high-impedance state (which you are calling 'input mode' here), the peripheral can also send a '0' without damaging the port (or leave it in high-impedance state, which is a de-facto '1' due to the pullup).

In this way, both sides of the connection can be configured to be inputs or outputs without damaging each other by driving opposing values.

However, data transfer speeds suffer because the pullup resistor has a slow transition time.

I guess you’re right! This explains the behavior I’m seeing. I’ll insert pull-ups and try again.

Update:
No, doesn't change anything. I also saw that the pins are already configured to have weak pull-ups. Btw. if I move slide-switch [1] in the ON position I do see HDMI_LRCLK on USERIO[5]. Only my own signals never appear when I put the slide-switch[1] back in the OFF position.

Okay, got it working. There was a problem with my design. USER_OUT/IN work as expected. Visible on Logic Analyser both direct and via 5v level shifter.

Glad to hear you got it working !