MiSTer FPGA Forum

Hello all

I want to do a couple of SDRAM HW modules myself (I already have some soldering experience with my own PCBs), and I have a number of questions looking at the schematics and information of the three available designs (I used the link https://github.com/MiSTer-devel/Main_Mi ... mbly-(DIY)) , if anyone can throw some light please!!

1) Which SDRAM capacities are supported by each of the HW designs? I am interested in 64MB capacity but see no specific info there.
Looking at the schematics it seems I could solder either the 32MB or 64MB part in any of them. If I am right, then this would be as follows (can please confirm?):
- Universal 3.1 U: I can create a 32MB or 64MB part, just changing the U1, and leaving the rest of components as in the BoM.
- XS 2.2: As in universal, I can create a 32MB or 64MB part by soldering proper U1 chip, and leaving capacitors as in BoM
- XSD 2.5: I can solder 2 of 64MB parts for the usual 128MB. But... can I just solder U1A and have 64MB (leaving U1B unsoldered), with all of the capacitors soldered? I guess the inverter is only needed if I want to add U1B later. And, due to mismatch in capacitor values, Should I use 0.1uF capacitors if I only solder U1A?
- XSD 2.5: I guess that as well, I can solder 2 of 32MB to create a 64MB card. Price-wise, this makes sense to me as 2x256MBIT Winbond chips are much cheaper than one Alliance 512MBIT chip.

2) I guess the pinout of the 2x20 pin connector is the same regardless of any of the three models. But I see some mistakes in the PDF with the schematics. Can someone confirm which of the three is the right labeling?
- UNI 3.1U vs XSD 2.5: The DQ0 pin is in same row as the CAS pin with XSD 2.5 schematic but it is swapped with RAS in the UNI schematic
- XS 2.2 vs XSD 2.5: Same with DQ0 pin and CAS pin, for example. There are several pins like that.
- XS 2.2 vs UNI 3.1U: The DQ14 is in different row respect DQ0 in each schematic.

3) XSD 2.5 There is a mismatch between the capacitors in the PDF schematic, and in the web page. The schematic says all are 1uF, but the web page in "2. Order Components" combines 10uF, 1uF and 0.1uF values. Which is better?

4) I would prefer to use only straight connector 2x20 instead of angled one, in the believe that it will be more stable / higher speeds, at the expense of using more space (horizontal-outward), at least, this is what it says for the universal board. But, can I use XS design with straight connector as well? It seems to me that a 128MB part would be more stable with a straight connector (as I do not have the phisical boards yet, I can not measure myself and see if this is possible or not)

5) Why the universal design has three additional pins to connect to the Arduino-like header of the FPGA board, but the XS and XSD do not have such? (this is P2H/P2V/P2R in UNI 3.1U, it also appears in previous release of XS 1.1 as P2).

6) Final question, thank you for your patience if read all... which cores won't work if I use a 64MB design. Clearly, NeoGeo will not work but... is there any other core requiring 128MB?


thanks again for all the help

Partial answers by myself, still welcome any feedback confirming or correcting me, thank you!

1) For XSD 2.5, it seems I can solder U1A and leave U1B and U3 unpopulated. As well it seems I can either use 256MBIT or 512MBIT parts (so yes, I could create a 32+32MB module using XSD 2.5 saving 15-20€ compared to a 128MB option). What can not be done is to mix 256MBIT and 512MBIT parts in same module.

5) According to schematic, comparing XS 1.1 and 2.2, the clock enable is fixed to ground when connector is removed. The two additional pins (DQML and DQMH) I guess are enabled or not in the code (but I have not seen this, although do not know verilog)

Additional investigations:

2) I have used Intel schematic (https://software.intel.com/content/dam/ ... 849456.pdf), plus some TCL files in the MemTest utility - I have no idea of the language used, but it is readable (https://github.com/MiSTer-devel/MemTest ... ys/sys.tcl & https://github.com/MiSTer-devel/MemTest ... _sdram.tcl), plus the different SDRAM module schematics. With this, I got following table, which clarifies my questions but introduces some additional ones. Here the table:


The additional questions:
a) Unless I have missed something, most of the data lines DQ0..DQ7, D14, D15 seem swapped to me in sys.tcl (GPIO0) or in schematic (pin 1/2, 3/4, 5/6, 7/8 and 9/10 of Header 20x2). They seem ok to me in sys_dual_sdram.tc on GPIO1.

b) I have discovered that GPIO1 is enabled to hold a second SDRAM daughterboard as per the sys_dual_sdram.tcl file. Can someone confirm if this is functional? I did not see anyone using this.

daparix wrote: ↑Sun Jan 03, 2021 12:59 pm a) Unless I have missed something, all the data lines DQ0..DQ7 seem reversed to me in sys.tcl (GPIO0) or in schematic (pin 1/2, 3/4, 5/6 and 7/8 of Header 20x2).

Order of DQ0..DQ7 and DQ8..DQ15 doesn't matter.

Ok thank you! So my question 2 is completely solved and the table above is right.

daparix wrote: ↑Sun Jan 03, 2021 12:59 pm b) I have discovered that GPIO1 is enabled to hold a second SDRAM daughterboard as per the sys_dual_sdram.tcl file. Can someone confirm if this is functional? I did not see anyone using this.

Yes, it's functional. NeoGeo has a version to use both modules, but i don't guarantee the current sources of NeoGeo still compatible. Anyway as a concept i've tried it and it's fully functional.

I need an excuse to use the extra GPIO pins on my digital IO board lol.