AUDIO Implementation (Amiga AND Framework)
Posted: Mon Mar 01, 2021 4:11 am
From the Amiga core, emu top module...
reg [15:0] aud_l, aud_r;
always @(posedge CLK_AUDIO) begin
reg [15:0] old_l0, old_l1, old_r0, old_r1;
old_l0 <= {ldata[14],ldata};
old_l1 <= old_l0;
if(old_l0 == old_l1) aud_l <= old_l1;
old_r0 <= {rdata[14],rdata};
old_r1 <= old_r0;
if(old_r0 == old_r1) aud_r <= old_r1;
end
Whatta F..... IS this?!
What are you doing? Delaying the audio signal like a pipe, and then cancel out amplitude climbs and falls, so to only update output audio when the amplitude settles for a couple of clocks (is the same)... if i understand the code correctly?
WHY?! I see the same error (or feature) in the main SYS framework too...
Also, it is not correct to take a 15 bit input signal and just sign extend it to 16 bits! Then you get half the volume out you are supposed to have, also, if the minimig core makes 16 bits sound output (which is also wrong btw, should be 9bits PWMd volume), then why at the current 16 bit version does it only output 15 of those bits?? you loose the LSB in the precission too, that way.
I see, i must fix both the minimig core AND the sys framework, the audio parts...
Question is... what kind of reception will it get. Will it get merged? Will it be understood? Do you see that the audio implmentation systemwide is wrong?
Not to be ungreatful, Mr. Sorgerlig, you are a genious, and you have done a remarkable superb job, beyond words, i admire your genious, i am very greatful to you too, BUT... you appearantly are no audio man. Try is you might.
I will look in to the audio code and overhaul what i can, as good as i can understand the current code in it's depths, what it's really doing... or atleast is trying to do, incorrectly.
Also another issue... you can't mix two or three 16 bits streams and truncate the result to 16 bits... you loose bit precission! You get a quarter output volume from all sources... as 3 x 16bits mixed is 18bits with one 16bit channel to spare for mixing.
What we need, is 20bit HDMI audio output, but i don't know how to do that. The hdmi clock and all that...
20 bits is needed in the sys framework for headroom for mixing from all cores! Really!
I am working on a new amiga iir filter module btw... this time pipelined, but im having some trouble with the recursives in the pipeline yet... it works... but output one interleaved sample too much inbetween...
This pipeline version to be able to up the clock... have had constraining trouble with my past implementations.. both monolith and multicycle...
So anyway.... i am now going to overhaul paula for pwm volume and 9 bit output, connect it to my filter in the minimig_top, shift the 9bit output up to 16 (which is the correct thing to do) the into the filter, and 16bit out from the filter, unfucked by the code above (DELETE) and rewrite, and feed the 16 bits filtered audio directly once per audio clock, untouched!
Then i will gut the framework for the same strange behaviour, and also look into the mixing and stuff..
To calm myself a little... why was it done this way? the delay with update on only alike samples?
Is it because of the frame delay in the video? 2 frames delay? is it out of a wrong understanding of audio
Why?
Also the strange only let through alike samples behaviour....
Iam pulling my hears out here, reading the code.... Iwe done audio for years!
Anyway.... what is this.. can you explain your thoughts on the code... why it is so, what you were trying to do?
You, get my 20bits hdmi audio out... and i will do the rest....
All cores should be updated after this fix.
Kindly...
Ole.
reg [15:0] aud_l, aud_r;
always @(posedge CLK_AUDIO) begin
reg [15:0] old_l0, old_l1, old_r0, old_r1;
old_l0 <= {ldata[14],ldata};
old_l1 <= old_l0;
if(old_l0 == old_l1) aud_l <= old_l1;
old_r0 <= {rdata[14],rdata};
old_r1 <= old_r0;
if(old_r0 == old_r1) aud_r <= old_r1;
end
Whatta F..... IS this?!
What are you doing? Delaying the audio signal like a pipe, and then cancel out amplitude climbs and falls, so to only update output audio when the amplitude settles for a couple of clocks (is the same)... if i understand the code correctly?
WHY?! I see the same error (or feature) in the main SYS framework too...
Also, it is not correct to take a 15 bit input signal and just sign extend it to 16 bits! Then you get half the volume out you are supposed to have, also, if the minimig core makes 16 bits sound output (which is also wrong btw, should be 9bits PWMd volume), then why at the current 16 bit version does it only output 15 of those bits?? you loose the LSB in the precission too, that way.
I see, i must fix both the minimig core AND the sys framework, the audio parts...
Question is... what kind of reception will it get. Will it get merged? Will it be understood? Do you see that the audio implmentation systemwide is wrong?
Not to be ungreatful, Mr. Sorgerlig, you are a genious, and you have done a remarkable superb job, beyond words, i admire your genious, i am very greatful to you too, BUT... you appearantly are no audio man. Try is you might.
I will look in to the audio code and overhaul what i can, as good as i can understand the current code in it's depths, what it's really doing... or atleast is trying to do, incorrectly.
Also another issue... you can't mix two or three 16 bits streams and truncate the result to 16 bits... you loose bit precission! You get a quarter output volume from all sources... as 3 x 16bits mixed is 18bits with one 16bit channel to spare for mixing.
What we need, is 20bit HDMI audio output, but i don't know how to do that. The hdmi clock and all that...
20 bits is needed in the sys framework for headroom for mixing from all cores! Really!
I am working on a new amiga iir filter module btw... this time pipelined, but im having some trouble with the recursives in the pipeline yet... it works... but output one interleaved sample too much inbetween...
This pipeline version to be able to up the clock... have had constraining trouble with my past implementations.. both monolith and multicycle...
So anyway.... i am now going to overhaul paula for pwm volume and 9 bit output, connect it to my filter in the minimig_top, shift the 9bit output up to 16 (which is the correct thing to do) the into the filter, and 16bit out from the filter, unfucked by the code above (DELETE) and rewrite, and feed the 16 bits filtered audio directly once per audio clock, untouched!
Then i will gut the framework for the same strange behaviour, and also look into the mixing and stuff..
To calm myself a little... why was it done this way? the delay with update on only alike samples?
Is it because of the frame delay in the video? 2 frames delay? is it out of a wrong understanding of audio
Why?
Also the strange only let through alike samples behaviour....
Iam pulling my hears out here, reading the code.... Iwe done audio for years!
Anyway.... what is this.. can you explain your thoughts on the code... why it is so, what you were trying to do?
You, get my 20bits hdmi audio out... and i will do the rest....
All cores should be updated after this fix.
Kindly...
Ole.