MiSTer FPGA Forum

Hi guyz, I was wondering if it's possible to have savestate for all the consoles core??? Thanks

Mr BIG

Its most likely technically possible on most console cores, but it would require so much work. I'm really hoping for save states on NES at the very least for an actual home console.

If done on a one-by-one basis, it won't be worthwhile.
There is some discussion about how this might be viable as a framework option (which would dramatically reduce per-core effort), but it's not yet even in the proof-of-concept stage.

Don't expect anything soon.

For having general savestates, all of these things MUST be working:
- read access to all registers and blockrams from HPS, not clear if that is even supported for the Cyclone 5.
- write access to all registers and RAMs at runtime (have never seen that feature for any FPGA)

Reading back ALL data will then take approximatly as long as downloading a bitfile, so assume ~10 seconds for creating or loading a savestate with this method.


But that's just the prequisite. Each core still needs to be prepared: it must be able to pause.
Turning off clock alone isn't enough, as it can be right in the middle of a transaction, e.g. reading external memory.

And for most cores it is more difficult to implement pause than reading back important registers/RAMs for a savestate,
as they were never designed to support pause.


So overall, I guess we have to live with implementing it for every core for quiet some time, if not forever.

I don't talk about a general one (sorry for the misunderstanding) I'm talking about one by one core savestate , should be more possible

Mr BIG

It was done on the fpga flash carts. it should be possible.
It's buggy on the flash carts, so don't expect it being stable.
I hear emulators do it differently then what it would be for a fpga core. We can only wait and see what the dev's can do.
It would be pretty cool thou. maybe saveslot slots so we don't have to deal with just one.

Lynx, GB(C) and GBA already have savestates that are stable with several slots.
So it is possible and mainly work to be done.

The method i used on this cores would work on any core that:
- is not at the very edge of timing or ressources (hello AO486)
- has a pause function

I will most likely add it to another 1-2 cores this year.

If someone wants to prepare a core with stable pause feature to motive me to add savestates there, feel free

I'm not good enough for this kind of stuff ^^, better on steel work , but I think I can wait and salute the efforts of community, I helped in a way by sending some pcb to jotego for developing new cores

Mr BIG

Can't wait for more save state cores. Hopefully snes is next?