When you drive 1's and 0's to the USER_IO port the signals are respectively high-Z and GND.
This means that you need to use a pull-up resistor to pull high-Z to 3.3V. And because of parasitic capacitance on the IO board this means the serial bandwidth is limited to 150kHz.
Why not drive real 1's instead? Is is okay to replace the following in sys_top.v?
What is your goal ?
The serial bandwidth can be higher than that with a slightly more aggressive pull-up resistor - 4K should not be a problem, which has a rise time of something like 2 microseconds (can't remember - this was some time ago).
They are configured for open-drain so that communication can take place bi-directionally, and because SNAC wiring is different for each core, implying that each data line is sometimes input and sometimes output.
If you drive a voltage out one of the pins which is then shorted to ground on the device attached, that's not going to be a good long-term strategy.
So while you can drive '1's, you should give thought as to what the consequences would be, and whether it is safe for the DE10-Nano and the device connected to it.
In the normal setup I can drive an SPI with approx 150kHz which is roughly 15KB/second including some overhead to a SPI USB interface.
After changing sys_top into outputting real 1’s and 0’s I do 2Mhz or around 200KB/sec.
So changing this creates at least 12 times the bandwidth.
I guess driving Z’s in stead of 1’s was chosen to be able to do bidirectional communication and indeed to protect the nano. But if you know what your doing and create your own extensions you can go much faster.