MiSTer FPGA Forum

I saw this very old article and was wondering if a Pentium would be possible in a future revision AO486:

https://www.eecg.utoronto.ca/~yiannac/docs/fpga07.pdf

The article also shows the used resources on the used FPGA Xilinx FPGA. Link to FPGA doc. They used the XC4VLX200.
https://www.xilinx.com/support/document ... /ds112.pdf

Perhaps the used FPGA code is floating on the internet somewhere.

Do not forget that such a system emulate just the Pentium and not anything else. It just plugs into the motherboard socket. To be usable with MISTer you would have to add to the core all the support chips necessary.

Yes I know but I’m just exploring if we could end up with AO486 with Pentium level performance on Mister. That would run every 486 and older games at a locked framerates with high quality settings. I know early 3D games are probably impossible but running games like Duke Nukem 3D at locked framerates would be awesome.

The ao486 core is really quite tight right now. There would need to be a fair bit of optimization - which is not clear how much savings would result from how much effort... so while it might be possible, don't expect it anytime soon.

To try and put into perspective: the 486SX which we have in ao486 uses 1.2 million transistors, the 486DX (with FPU) has 1.85 million transistors, and the first P60 Pentiums (basically two 486DXs on a die) had 3.1 million transistors. And as dshadoff has pointed out, the current ao486 core is a tight squeeze!

Perhaps the only way performance could be increased is by running a mix of FPGA with HPS. Theoretically it should be possible to run CPU code on a single ARM core which has it's own NEON FPU and using the other ARM core for the Linux OS instead of both ARM cores. It would probably be too much work to implement and the OS would run more slowly but I hope something like this will be possible in the future. Freeing up the FPGA for a simple 3D graphics implementation like a S3 Virge, NV-1, 3DFX SST96 (Voodoo Rush) or something along those lines.

Don´t forget that all inputs from usb goes trough the ARM.
Which means that if one core is suddenly gone from the "mister backend" most likely will mean much higher latency on all inputs.

If for example SNAC was used as input instead it would not affect it at all but SNAC will take FPGA resources instead.