MiSTer FPGA Forum

I knew about the "OSSC 2" for quite some time now but totally missed that bit where they hint it very likely will be able to run MiSTer cores (it's Cyclone 5 based). I'm a CRT user so don't need the "old' OSSC, but they also say Pro will be able to downscale modern sources to 240p/480i for dispalying on CRTs. In conjunction with the ability to run MiSTer cores it's something which makes me rather interested. It's shaping up to be quite a powerhouse, though the price will most likely pack a powerful punch too (and I don't think it will be available anytime soon).

What do you think, how feasible is this core running ability?

The VGA scaler already kind of does that, and shows the limitation of the process: most platforms requiring it are computers, with heavy text based interfaces, and losing most of the pixels makes those really hard to decypher.
I am guessing the OSSC Pro could work some filter around it, but it will probably not solve the reasonable usability issue.

There is no guarantee that WIP OSSC pro will be able to run any MiSTer cores, its FPGA won't probably have any ARM CPU, any port would need significant efforts.

MiSTer scaler was optimised for up-scaling. Downscaling support is basic to save FPGA resources (bilinear only).
Moderate vertical downscaling in the output pipeline and interlaced output could have some use for CRT amateurs though.

Maybe you can get some MIST cores to run, that doesn't have an ARM either.

Newsdee wrote: ↑Sat May 30, 2020 11:39 am Maybe you can get some MIST cores to run, that doesn't have an ARM either.

MiST has.

Sorgelig wrote: ↑Sat May 30, 2020 4:45 pm MiST has.

Not on the FPGA chip itself, and not running at 800 MHz.
It is much sinpler than what is on the DE10-Nano.

Grabulosaure wrote: ↑Fri May 29, 2020 8:41 pm There is no guarantee that WIP OSSC pro will be able to run any MiSTer cores, its FPGA won't probably have any ARM CPU, any port would need significant efforts.

MiSTer scaler was optimised for up-scaling. Downscaling support is basic to save FPGA resources (bilinear only).
Moderate vertical downscaling in the output pipeline and interlaced output could have some use for CRT amateurs though.

They are building it around a Cyclone V with ARM SoC. It's a variation of the DE-10's chip.

Maybe you can run cores on it but I would think it would be more interesting to design MiSTer cores to push it's limit using native output resolution and offloading the scaler to the OSSCpro or other functions. For example if the MiSTer just has enough space for a tower of power 32x+SegaCD+Genesis then you can have the OSSCpro do the adaptive blending and upscaling or other functions the MiSTer currently does. Or possibly maybe have the 32x core on the OSSCpro leaving the SegaCD and Genesis on the MiSTer. Either way the OSSC pro will be interesting and a must buy if you like retro consoles as it will fully replace the Framemister and will introduce a tone of interesting features and open the OSSC to output higher resolutions like 1440p.