MiSTer FPGA Forum

Posted: **Wed Apr 21, 2021 3:03 pm**

In the topic "MiSTer updates and changelog" @Sorgelig say

Hardware - New SDRAM v2.9:

Could you post pictures of the new project? will it be possible to change a v2.5 to v2.9 project?

Posted: **Wed Apr 21, 2021 3:31 pm**

3D render of the rear of the updated SDRAM memory module.

: 1.jpg (102.47 KiB) Viewed 22821 times

Posted: **Wed Apr 21, 2021 4:39 pm**

Does that new pin header have to be done in a reflow oven? Don't see how you could fit a soldering iron in there.

Posted: **Wed Apr 21, 2021 5:54 pm**

Is this to be sold or still R&D ?

Posted: **Wed Apr 21, 2021 9:41 pm**

Looks like a routing error on this version, pin 1&3 are VDD supply pins, but share a capacitor. Pin 37 is a signal pin tied to VDD, but has a capacitor which probably should be on one of the supply pins.

Posted: **Wed Apr 21, 2021 10:28 pm**

Sectorseven wrote: ↑Wed Apr 21, 2021 4:39 pm Does that new pin header have to be done in a reflow oven? Don't see how you could fit a soldering iron in there.

You probably could with a thin enough tip. Elongated Shape J or Shape SB T12 tips could do this if they are thin enough.

Posted: **Wed Apr 21, 2021 11:10 pm**

It would normally be done in a reflow oven or with a hot air rework station. Very fast. Just perhaps not as mechanically strong.

Posted: **Thu Apr 22, 2021 4:04 am**

Preferable design for builders overall, because trimming the through hole headers to the right height wasn't that easy. Baking on some solder paste is easier, and most of the resellers already use reflow all of the time anyways.

My main problem so far is... I have no experience with that header and can't easily find it online!

Was just curious to build up a BOM and store it away for awhile, and everything is sold out!

EDIT: Nvm spoke too soon!

https://www.aliexpress.com/i/4000318372 ... 07c8704-17

Posted: **Thu Apr 22, 2021 4:27 am**

Would this design be more compatible with PCB fabrication shops? If so, it should drive down cost...

Posted: **Thu Apr 22, 2021 4:52 am**

The LDO used is in a nonstandard package. The LM1117 does not come in SOT89. Looking for this I only find Chinese brands. It’s not the first time I see the Mister project using these kinds of low quality/fake components.

Posted: **Thu Apr 22, 2021 5:05 am**

C-R-T wrote: ↑Thu Apr 22, 2021 4:52 am The LDO used is in a nonstandard package. The LM1117 does not come in SOT89. Looking for this I only find Chinese brands. It’s not the first time I see the Mister project using these kinds of low quality/fake components.

huh? HTC Korea is a Chinese Brand?

https://lcsc.com/product-detail/Dropout ... 26021.html

https://lcsc.com/product-detail/Dropout ... 26020.html

Posted: **Thu Apr 22, 2021 5:08 am**

Sorry, I should have said low quality brand. Pretty much anything you can find on LCSC.

Posted: **Thu Apr 22, 2021 5:10 am**

Just because something isn't Texas Instruments doesn't make it bad though.

I get what you are saying, but the reaction was pretty out of proportion lol

Also...

https://careers.ti.com/locations/#asia

TI doesn't mean it's not made in China.

Posted: **Thu Apr 22, 2021 7:28 am**

We need a part number/source for the 40pin RA connector. I've been previously searching for something like that, but couldn't find it through the 'normal' channels.

Posted: **Thu Apr 22, 2021 7:30 am**

Thanks for the new version, I have to build a few for my MiSTers!

What is the correct layer stackup of the PCB for controlled impedance? JLCPCB supports two stackups, JLC7628 with 0.2mm prepreg and JLC2313 with 0.1mm prepreg, which one to use?

Also what capacitor configuration is recommended for this version?

Posted: **Thu Apr 29, 2021 9:49 am**

I'd be interested in answers from someone knowledgable in electronics to MickGyvers questions as well. My electronics knowledge is not very deep

From what I see, there are two new ones in the top row which used to be 10uF, 0.1uF - 10uF, 0.1uF for the 2.5 module.
Given that my understanding is that they are bypass capacitors, I'd guess that this should probably either be 10uF, 1uF, 0.1uF or 10uF, 0.1uF, 0.1uF for each chip or maybe even something like 10uF, 0.1uF, 100nF. Not sure what is better here.

The C15 one probably should be 10uF as stated in the schematic as it matches the capacitance stated in the data sheet of LM1117 for the input.

About the layer stackup, my guess would be that uncontrolled is fine. From what I have read, controlled impedances should normally be marked as such in the schematic.

Again, I have little idea what I'm talking about and would love to hear some opinions from someone who knows better, I just want to get the discussion going

Posted: **Fri May 14, 2021 1:18 pm**

Is anybody selling these new versions yet?

Posted: **Fri May 14, 2021 1:46 pm**

bnz99 wrote: ↑Thu Apr 29, 2021 9:49 am I'd be interested in answers from someone knowledgable in electronics to MickGyvers questions as well. My electronics knowledge is not very deep

From what I see, there are two new ones in the top row which used to be 10uF, 0.1uF - 10uF, 0.1uF for the 2.5 module.
Given that my understanding is that they are bypass capacitors, I'd guess that this should probably either be 10uF, 1uF, 0.1uF or 10uF, 0.1uF, 0.1uF for each chip or maybe even something like 10uF, 0.1uF, 100nF. Not sure what is better here.

The C15 one probably should be 10uF as stated in the schematic as it matches the capacitance stated in the data sheet of LM1117 for the input.

About the layer stackup, my guess would be that uncontrolled is fine. From what I have read, controlled impedances should normally be marked as such in the schematic.

Again, I have little idea what I'm talking about and would love to hear some opinions from someone who knows better, I just want to get the discussion going

From what I have figured out, the layer stackup should be JLC7628 (0.2mm prepreg), at least that seem to have been the one for the older version. C15=10µF and I will try this for the capacitors when I get the PCBs (1µf for the "new" caps):

Code: Select all

top row: 10µf, 0.1µf, 1µf, 10µf, 0.1µf, 1µf
bottom row: 10uf, 1µf, 1µf, 10µf, 10µf, 1µf, 1µf, 10µf

Posted: **Fri May 14, 2021 6:39 pm**

Newsdee wrote: ↑Fri May 14, 2021 1:18 pm Is anybody selling these new versions yet?

I know that Ultimatemister is.

Posted: **Sat May 15, 2021 1:22 am**

dmckean wrote: ↑Fri May 14, 2021 6:39 pm I know that Ultimatemister is.

It's listed as 2.9, but the picture looks different. Has anybody ordered it yet?

Posted: **Sat May 15, 2021 6:40 am**

Newsdee wrote: ↑Sat May 15, 2021 1:22 am
dmckean wrote: ↑Fri May 14, 2021 6:39 pm I know that Ultimatemister is.
It's listed as 2.9, but the picture looks different. Has anybody ordered it yet?

looks modified to still use a thru hole header

Posted: **Sat May 15, 2021 9:17 am**

Please excuse my ignorance, but having only just bought a v2.5 128Mb SDRAM, why is a new revision necessary? In layman's terms, Is there something wrong with the 2.5?

Posted: **Sat May 15, 2021 9:52 am**

Fuzzball wrote: ↑Sat May 15, 2021 9:17 am Please excuse my ignorance, but having only just bought a v2.5 128Mb SDRAM, why is a new revision necessary? In layman's terms, Is there something wrong with the 2.5?

I think they are prone to being faulty. Problems were discovered when Jotego released his CPS1.5 or CPS2 beta and around 20% of users had problems if I remember correctly.

Posted: **Sat May 15, 2021 9:58 am**

warham wrote: ↑Sat May 15, 2021 6:40 am looks modified to still use a thru hole header

I think it's just that they're still using photos of the 2.5 module.

Fuzzball wrote: ↑Sat May 15, 2021 9:17 am Please excuse my ignorance, but having only just bought a v2.5 128Mb SDRAM, why is a new revision necessary? In layman's terms, Is there something wrong with the 2.5?

For most people the 2.5 module works fine. Some people have had issues with the 2.5 module and certain cores which make heavier demands of the SDRAM (mostly Jotego's CPS cores). These have been attributed to insufficient power conditioning and suspect signal integrity with the 2.5 module, hence the redesign. Nonetheless the 2.5 module works fine for an awful lot of people, so unless you encounter problems with yours there's no need to worry about it.
(Even with the redesign, the FPGA and SDRAM module are still separated by a 40-pin header, and the DE10-nano half of it is still through-hole - so the signal path is still the high-speed-electronics equivalent of a dirt track; there are just somewhat fewer potholes than before.)

Posted: **Sat May 15, 2021 11:53 am**

Fuzzball wrote: ↑Sat May 15, 2021 9:17 am Please excuse my ignorance, but having only just bought a v2.5 128Mb SDRAM, why is a new revision necessary? In layman's terms, Is there something wrong with the 2.5?

if you run memtest by jotego and everything runs fine, like it did for me, a new version is not necessary for you

Posted: **Mon May 17, 2021 2:57 pm**

There is a better test also by Jotego

https://github.com/antoniovillena/MiSTe ... p?raw=true

If your SDRAM module passes all 8 rbf you won't have future problems with your module

Posted: **Tue May 18, 2021 9:49 am**

warham wrote: ↑Sat May 15, 2021 6:40 am
Newsdee wrote: ↑Sat May 15, 2021 1:22 am
dmckean wrote: ↑Fri May 14, 2021 6:39 pm I know that Ultimatemister is.
It's listed as 2.9, but the picture looks different. Has anybody ordered it yet?
looks modified to still use a thru hole header

Of course not. We use smd design for some months. I don't use the TH header anymore. Iv'e been testing this new rams for months.

I will do stock photos and update site photos soon, sorry no time yet.

Posted: **Sat Jun 05, 2021 5:17 am**

antoniovillena wrote: ↑Mon May 17, 2021 2:57 pm There is a better test also by Jotego

https://github.com/antoniovillena/MiSTe ... p?raw=true

If your SDRAM module passes all 8 rbf you won't have future problems with your module

Could I get an explanation of how to run these tests? Is it just running each individual core and run the ghouls rom and if it passes the boot up tests, it's considered a pass?

Posted: **Sat Jun 05, 2021 6:41 am**

Has anyone here already tested a specific capacitor setup for a longer period? I'll have all my parts ready next week to build one of those new 2.9 boards.

Posted: **Sun Jun 06, 2021 9:00 am**

eightbitminiboss wrote: ↑Sat Jun 05, 2021 5:17 am
antoniovillena wrote: ↑Mon May 17, 2021 2:57 pm There is a better test also by Jotego

https://github.com/antoniovillena/MiSTe ... p?raw=true

If your SDRAM module passes all 8 rbf you won't have future problems with your module
Could I get an explanation of how to run these tests? Is it just running each individual core and run the ghouls rom and if it passes the boot up tests, it's considered a pass?

Yes. If passes all cores with ok on boot up tests the memory is ok

MiSTer FPGA Forum

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