MiSTer FPGA Forum

i finally have my MiSTer up and working and playing with the ST core. As a huge fan of Atari/TOS machines that I used many years, I'd like to push the core capabilities towards the higher end Atari/TOS machines. Actually, the result should be rather an generic TOS machine, that would have fast CPU, enough RAM, high resolution color, than (cycle) exact simulation of a particular machine (forget Falcon, for now).

There are a couple of modifications that could be done with not that much effort:
- TG68 core for 020+ instruction support and better speed (MiST core has already added experimental support for that)
- FastRAM above 16MB thanks to 32bit core

Then a bit more complicated parts:
- network driver for mintnet (and perhaps stik/sting, too) as s wrapper for underlying linux system
- new graphics mode(s) either by implementing part of VIDEL chip to support 256 and 16bit mode in various resolutions AND TOS4.4 that has support for these modes (not sure if EmuTOS already supports these modes) or by a "graphic card" using a fvdi driver (can be borrowed from Aranym)
- generic Xbios audio like on Aranym or Clones that use SB cards

Long term goals:
- Falcon SDMA + 16bit audio subystem
- Falcon DSP (using Aranym or Hatari software in hybrid emulation?)
- 68030 MMU (hybrid emulation?)
- Falcon core as a byproduct?

So, firstly I'd like to ask the author(s) of current MiSTery port, if some of the improvements (at least port the TG68 from the MiST core) is planned or even in progress, otherwise I'l try to do it myself.

It will be great to have a Roadmap.

You are free to improve this core.
I've ported this core to MiSTer, but have no much interest in Atari ST in general. So developer who is ST fan would be good.

Like the plan! If you have a Patreon I will be more than happy to support the development. Both Atari ST and X68000 developments are for me the best complement to the already excellent Amiga core!
Really great to see Atari interest developing in the Mister community!!

Ok then. I'll try to do something. In fact in meantime I already tried to hack TG68k CPU into core, but didn't pass event the HW init (white screen only). I have to learn all the Quartus, Signal Tap and (system) Verilog stuff first, because I came from VHDL and Xilinx world

Sorgelig wrote: ↑Sat May 08, 2021 5:39 pm You are free to improve this core.
I've ported this core to MiSTer, but have no much interest in Atari ST in general. So developer who is ST fan would be good.

I have one more question. Do you plan to continue to port changes from MiST core or at least fix issues of the current code (I noticed not all memory configurations do work and Viking output rendering looks half broken)? I definitely don't want to interfere with your work.

I think i've ported already all changes (may be very recent changes aren't ported yet). You are free to port changes yourself. I'm currently not working on this core.

Could also try the hybrid stuff that I'm playing with on the Amiga core, let me know when you get to that point (if interested).

edit: errr, saw you already mentioned that in the first post