MiSTer FPGA Forum

Is it possible to use the low PHI clock cycle for RAM access with the Arlet 6502 core - as in a real 6502 chip? Most cores (maybe all) I have seen just split the VRAM circuitry from the operation of the 6502 core, but I'd be interested to know if you can indeed mimic actual hardware ram/rom timing or it's not actually possible.

Thanks,
Nick

The answer by the way, is no, it's not.

I'm going to do an upcoming video about how to get over this with the 6502 core.

FPGA (Quartus?) seems to dislike using signals from components as clocks and complains about them. (unlike real hardware)

instead I find you have to pick a higher clock to clock everything related on, and use enable signals to only select the relevant clock pulses.