Can be added new core_type for debugging purpouses to the MiSTer framework?

[RndMnkIII]

Hi, the following verilog code in sys_top.v can be expanded to include a debug core version code that can be liberate GPIO 01 header pins for developer ussage and not reserved for DUAL_SDRAM?

Code: Select all

`ifdef DUAL_SDRAM
	wire  [7:0] core_type  = 'hA8; // generic core, dual SDRAM.
`else
	wire  [7:0] core_type  = 'hA4; // generic core.
`endif

// HPS will not communicate to core if magic is different
wire [31:0] core_magic = {24'h5CA623, core_type};

cyclonev_hps_interface_mpu_general_purpose h2f_gp
(
	.gp_in({~gp_out[31] ? core_magic : gp_in}),
	.gp_out(gp_out)
);

[Sorgelig]

For debug purpose you can do whatever you want. I don't see the topic of discussion. Debugging is very wide term. For example i use SignalTap from Quartus to monitor any signal inside the core i want. Never needed any external GPIO for that purpose.
As for GPIO - it can be used for different purposes and will require different setups. Some needs input, some output, some bidir. May be fast input register is required, may be fast output, etc, etc...
For serial debug i/o existing USER I/O with 7 GPIOs should be fine too.

GPIO 01 is used on I/O board for VGA and analog audio. Somehow it's also debug usage. You can exclude Scaler in latest framework from compilation to save the time, and then use VGA output.
So it's not like completely unused.

[Sorgelig]

Saw your other topic about the same question with more details.
Your case is specific to your own purpose. So if you want to use additional board, then you have to create a proper pin description according to addon board and modify framework to access those pins.
There is no one solution to fit everything.