Can be added new core_type for debugging purpouses to the MiSTer framework?
Posted: Thu Jun 04, 2020 11:27 am
Hi, the following verilog code in sys_top.v can be expanded to include a debug core version code that can be liberate GPIO 01 header pins for developer ussage and not reserved for DUAL_SDRAM?
Code: Select all
`ifdef DUAL_SDRAM
wire [7:0] core_type = 'hA8; // generic core, dual SDRAM.
`else
wire [7:0] core_type = 'hA4; // generic core.
`endif
// HPS will not communicate to core if magic is different
wire [31:0] core_magic = {24'h5CA623, core_type};
cyclonev_hps_interface_mpu_general_purpose h2f_gp
(
.gp_in({~gp_out[31] ? core_magic : gp_in}),
.gp_out(gp_out)
);